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Merge branch 'master' into master

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Rodrigo A. Melo 2020-02-03 11:07:51 -03:00 • committed by GitHub
commit 665a967d87
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10 changed files with 367 additions and 4 deletions
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32
tests/arch/ecp5/opt_lut_ins.ys Normal file
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read_ilang << EOF
module \top
wire input 1 \A
wire input 2 \B
wire input 3 \C
wire input 4 \D
wire output 5 \Z
cell \LUT4 $0
parameter \INIT 16'1111110011000000
connect \A \A
connect \B \B
connect \C \C
connect \D \D
connect \Z \Z
end
end
EOF
read_verilog -lib +/ecp5/cells_sim.v
equiv_opt -assert -map +/ecp5/cells_sim.v opt_lut_ins -tech ecp5
design -load postopt
select -assert-count 1 top/t:LUT4
select -assert-count 0 top/w:A %co top/t:LUT4 %i
select -assert-count 1 top/w:B %co top/t:LUT4 %i

8
tests/arch/gowin/mux.ys
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@ -18,13 +18,13 @@ proc
equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 4 t:LUT4
select -assert-count 4 t:LUT*
select -assert-count 2 t:MUX2_LUT5
select -assert-count 1 t:MUX2_LUT6
select -assert-count 6 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux8
@ -35,7 +35,7 @@ cd mux8 # Constrain all select calls below inside the top module
select -assert-count 11 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top mux16
@ -46,4 +46,4 @@ cd mux16 # Constrain all select calls below inside the top module
select -assert-count 20 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D
select -assert-none t:GND t:VCC t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D

25
tests/arch/xilinx/opt_lut_ins.ys Normal file
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read_ilang << EOF
module \top
wire width 4 input 1 \A
wire output 2 \O
cell \LUT4 $0
parameter \INIT 16'1111110011000000
connect \I0 \A [0]
connect \I1 \A [1]
connect \I2 \A [2]
connect \I3 \A [3]
connect \O \O
end
end
EOF
equiv_opt -assert -map +/xilinx/cells_sim.v opt_lut_ins -tech xilinx
design -load postopt
select -assert-count 1 t:LUT3

23
tests/opt/opt_lut_ins.ys Normal file
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read_ilang << EOF
module \top
wire width 4 input 1 \A
wire output 2 \Y
cell $lut \lut
parameter \LUT 16'1111110011000000
parameter \WIDTH 4
connect \A \A
connect \Y \Y
end
end
EOF
equiv_opt -assert opt_lut_ins
design -load postopt
select -assert-count 1 t:$lut r:WIDTH=3 %i