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Merge pull request #1576 from YosysHQ/eddie/opt_merge_init

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opt_merge: discard \init of '$' cells with 'Q' port when merging
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Eddie Hung 2020-02-05 14:56:26 -08:00 • committed by GitHub
commit 505557e93e
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2 changed files with 65 additions and 1 deletions
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tests/opt/opt_merge_init.ys Normal file
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read_verilog -icells <<EOT
module top(input clk, i, (* init = 1'b0 *) output o, p);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffo (
.CLK(clk),
.D(i),
.Q(o)
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ffp (
.CLK(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 1 a:init=1'0
design -reset
read_verilog -icells <<EOT
module top(input clk, i, (* init = 2'b11 *) output [1:0] o);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ff1 (
.CLK(clk),
.D(i),
.Q(o[1])
);
\$dff #(
.CLK_POLARITY(1'h1),
.WIDTH(32'd1)
) ff0 (
.CLK(clk),
.D(i),
.Q(o[0])
);
endmodule
EOT
opt_merge
select -assert-count 1 a:init=2'bx1