3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00

iopadmap: move \init attributes from outpad output to its input

This commit is contained in:
Eddie Hung 2020-02-13 12:05:14 -08:00
parent cb7bc6a12f
commit ebb11bcea4
2 changed files with 57 additions and 3 deletions

View file

@ -120,3 +120,40 @@ select -assert-count 1 g/t:iobuf
select -assert-count 1 h/t:ibuf
select -assert-count 1 h/t:iobuf
select -assert-count 1 h/t:obuf
# Check that \init attributes get moved from output buffer
# to buffer input
design -reset
read_verilog << EOT
module obuf (input i, (* iopad_external_pin *) output o); endmodule
module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule
module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule
module sub(input i, output o); endmodule
module a(input i, (* init=1'b1 *) output o);
sub s(.i(i), .o(o));
endmodule
module b(input i, oe, output o);
(* init=1'b1 *) wire w;
sub s(.i(i), .o(w));
assign o = oe ? w : 1'bz;
endmodule
module c(input i, oe, inout io);
(* init=1'b1 *) wire w;
sub s(.i(i), .o(w));
assign io = oe ? w : 1'bz;
endmodule
EOT
opt_clean
tribuf
simplemap
iopadmap -bits -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io
select -assert-count 1 a/c:s %co a/a:init=1'1 %i
select -assert-count 1 a/a:init=1'1
select -assert-count 1 b/c:s %co b/a:init=1'1 %i
select -assert-count 1 b/a:init=1'1
select -assert-count 1 c/c:s %co c/a:init=1'1 %i
select -assert-count 1 c/a:init=1'1