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verilog: fix $specify3 check

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This commit is contained in:
Eddie Hung 2020-02-12 12:16:01 -08:00
parent cb7bc6a12f
commit 7cfdf4ffa7
2 changed files with 18 additions and 7 deletions
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7
tests/various/specify.v
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@ -37,3 +37,10 @@ specify
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule
module test3(input clk, input [1:0] d, output [1:0] q);
specify
(posedge clk => (q +: d)) = (3,1);
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule