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Merge pull request #1656 from YosysHQ/eddie/ice40_abc9_warnings

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ice40: reduce ABC9 internal fanout warnings with a param for CI->I3
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Eddie Hung 2020-01-27 09:54:04 -08:00 • committed by GitHub
commit af8281d2f5
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6 changed files with 26 additions and 32 deletions
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27
tests/arch/ice40/ice40_opt.ys
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@ -1,23 +1,3 @@
read_verilog -icells -formal <<EOT
module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
parameter LUT = 0;
SB_CARRY carry (
.I0(A),
.I1(B),
.CI(CI),
.CO(CO)
);
\$lut #(
.WIDTH(4),
.LUT(LUT)
) lut (
.A({I0,A,B,I3}),
.Y(O)
);
endmodule
EOT
design -stash unmap
read_verilog -icells -formal <<EOT
module top(input CI, I0, output [1:0] CO, output O);
wire A = 1'b0, B = 1'b0;
@ -26,13 +6,14 @@ module top(input CI, I0, output [1:0] CO, output O);
// A[1]: 1100 1100 1100 1100
// A[2]: 1111 0000 1111 0000
// A[3]: 1111 1111 0000 0000
.LUT(~16'b 0110_1001_1001_0110)
.LUT(~16'b 0110_1001_1001_0110),
.I3_IS_CI(1'b1)
) u0 (
.A(A),
.B(B),
.CI(CI),
.I0(I0),
.I3(CI),
.I3(1'bx),
.CO(CO[0]),
.O(O)
);
@ -40,7 +21,7 @@ module top(input CI, I0, output [1:0] CO, output O);
endmodule
EOT
equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
equiv_opt -assert -map +/ice40/abc9_model.v -map +/ice40/cells_sim.v ice40_opt
design -load postopt
select -assert-count 1 t:*
select -assert-count 1 t:$lut