mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

hierarchy: Correct handling of wildcard port connections with default values

Browse source 
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-11-22 09:21:35 +00:00
parent a210675d71
commit 7e741714df
2 changed files with 25 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

11
tests/various/sv_implicit_ports.sh
View file

@ -54,3 +54,14 @@ module top(input [7:0] a, output [7:0] q);
endmodule
EOT
) 2>&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null
# Defaults
../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <<EOT
module add(input [7:0] a = 8'd00, input [7:0] b = 8'd01, output [7:0] q);
assign q = a + b;
endmodule
module top(input [7:0] a, output [7:0] q);
add add_i(.*);
endmodule
EOT