mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

xilinx: Add support for LUT RAM on LUT4-based devices.

Browse source 
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
This commit is contained in:
Marcin Kościelnicki 2020-02-03 18:37:28 +01:00 • committed by Marcelina Kościelnicka
parent d48950d92d
commit 89adef352f
5 changed files with 42 additions and 27 deletions
Download patch file Download diff file Expand all files Collapse all files

20
tests/arch/xilinx/lutram.ys
View file

@ -135,3 +135,23 @@ select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 2 t:RAM64M
select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
design -reset
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r -chparam A_WIDTH 4
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -family xc3s -noiopad
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 8 t:RAM16X1D
select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D