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Merge pull request #1650 from YosysHQ/eddie/shiftx2mux

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techmap LSB-first for compatible $shift/$shiftx cells
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Eddie Hung 2020-02-05 14:55:57 -08:00 • committed by GitHub
commit 6eb7e925a1
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4 changed files with 187 additions and 41 deletions
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6
tests/arch/ecp5/mux.ys
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@ -39,8 +39,8 @@ proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 12 t:L6MUX21
select -assert-count 34 t:LUT4
select -assert-count 17 t:PFUMX
select -assert-count 8 t:L6MUX21
select -assert-count 26 t:LUT4
select -assert-count 12 t:PFUMX
select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D

4
tests/arch/efinix/mux.ys
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@ -16,7 +16,7 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4
#select -assert-count 2 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D
@ -26,7 +26,7 @@ proc
equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 5 t:EFX_LUT4
#select -assert-count 5 t:EFX_LUT4
select -assert-none t:EFX_LUT4 %% t:* %D

110
tests/techmap/shiftx2mux.ys Normal file
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@ -0,0 +1,110 @@
read_verilog <<EOT
module sc1 (i1 ,
i2 ,
i3 ,
i4 ,
i5 ,
i6 ,
i7 ,
i8 ,
i9 ,
i10,
i11,
i12,
i13,
i14,
i15,
binary_out,
encoder_in,
enable
);
input [3:0] i1 ;
input [3:0] i2 ;
input [3:0] i3 ;
input [3:0] i4 ;
input [3:0] i5 ;
input [3:0] i6 ;
input [3:0] i7 ;
input [3:0] i8 ;
input [3:0] i9 ;
input [3:0] i10 ;
input [3:0] i11 ;
input [3:0] i12 ;
input [3:0] i13 ;
input [3:0] i14 ;
input [3:0] i15 ;
output reg [3:0] binary_out ;
input [3:0] encoder_in ;
input enable ;
always @ (*)
begin
binary_out = 0;
if (enable) begin
case (encoder_in)
4'h1 : binary_out = i1;
4'h2 : binary_out = i2;
4'h3 : binary_out = i3;
4'h4 : binary_out = i4;
4'h5 : binary_out = i5;
4'h6 : binary_out = i6;
4'h7 : binary_out = i7;
4'h8 : binary_out = i8;
4'h9 : binary_out = i9;
4'ha : binary_out = i10;
4'hb : binary_out = i11;/*
4'hc : binary_out = i12;
4'hd : binary_out = i13;
4'he : binary_out = i14;
4'hf : binary_out = i15;*/
endcase
end
end
endmodule
EOT
proc
pmux2shiftx
design -save gold
design -load gold
techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
abc -lut 6
select -assert-min 17 t:$lut
design -load gold
techmap
abc -lut 6
select -assert-count 16 t:$lut
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load gold
techmap -D NO_LSB_FIRST_SHIFT_SHIFTX
abc9 -lut 6
select -assert-min 17 t:$lut
design -load gold
techmap
abc9 -lut 6
select -assert-count 16 t:$lut
design -stash gate
design -import gold -as gold
design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter