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Merge pull request #1619 from YosysHQ/eddie/abc9_refactor
Refactor `abc9` pass
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commit
48f3f5213e
11 changed files with 1833 additions and 1410 deletions
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@ -291,3 +291,19 @@ module abc9_test035(input clk, d, output reg [1:0] q);
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always @(posedge clk) q[0] <= d;
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always @(negedge clk) q[1] <= q[0];
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endmodule
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module abc9_test036(input A, B, S, output [1:0] O);
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(* keep *)
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MUXF8 m (
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.I0(I0),
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.I1(I1),
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.O(O[0]),
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.S(S)
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);
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MUXF8 m2 (
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.I0(I0),
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.I1(I1),
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.O(O[1]),
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.S(S)
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);
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endmodule
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@ -39,6 +39,35 @@ design -load gold
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scratchpad -copy abc9.script.flow3 abc9.script
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abc9 -lut 4
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design -reset
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read_verilog <<EOT
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module top(input a, b, output o);
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(* keep *) wire w = a & b;
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assign o = ~w;
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endmodule
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EOT
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simplemap
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equiv_opt -assert abc9 -lut 4
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design -load postopt
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select -assert-count 2 t:$lut
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design -reset
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read_verilog -icells <<EOT
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module top(input a, b, output o);
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wire w;
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(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
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assign o = ~w;
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endmodule
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EOT
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simplemap
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equiv_opt -assert abc9 -lut 4
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design -load postopt
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select -assert-count 1 t:$lut
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select -assert-count 1 t:$_AND_
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design -reset
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read_verilog -icells <<EOT
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@ -14,6 +14,7 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load read
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hierarchy -top abc9_test028
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proc
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@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
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select -assert-count 1 t:unknown
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select -assert-none t:$lut t:unknown %% t: %D
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design -load read
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hierarchy -top abc9_test032
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proc
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@ -38,3 +40,16 @@ design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -seq 10 -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog -icells <<EOT
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module abc9_test036(input clk, d, output q);
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(* keep *) reg w;
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$__ABC9_FF_ ff(.D(d), .Q(w));
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wire \ff.clock = clk;
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wire \ff.init = 1'b0;
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assign q = w;
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endmodule
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EOT
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abc9 -lut 4 -dff
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