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Merge pull request #1619 from YosysHQ/eddie/abc9_refactor

Refactor `abc9` pass
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Eddie Hung 2020-01-27 13:29:15 -08:00 committed by GitHub
commit 48f3f5213e
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11 changed files with 1833 additions and 1410 deletions

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@ -291,3 +291,19 @@ module abc9_test035(input clk, d, output reg [1:0] q);
always @(posedge clk) q[0] <= d;
always @(negedge clk) q[1] <= q[0];
endmodule
module abc9_test036(input A, B, S, output [1:0] O);
(* keep *)
MUXF8 m (
.I0(I0),
.I1(I1),
.O(O[0]),
.S(S)
);
MUXF8 m2 (
.I0(I0),
.I1(I1),
.O(O[1]),
.S(S)
);
endmodule

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@ -39,6 +39,35 @@ design -load gold
scratchpad -copy abc9.script.flow3 abc9.script
abc9 -lut 4
design -reset
read_verilog <<EOT
module top(input a, b, output o);
(* keep *) wire w = a & b;
assign o = ~w;
endmodule
EOT
simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 2 t:$lut
design -reset
read_verilog -icells <<EOT
module top(input a, b, output o);
wire w;
(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b));
assign o = ~w;
endmodule
EOT
simplemap
equiv_opt -assert abc9 -lut 4
design -load postopt
select -assert-count 1 t:$lut
select -assert-count 1 t:$_AND_
design -reset
read_verilog -icells <<EOT

View file

@ -14,6 +14,7 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
design -load read
hierarchy -top abc9_test028
proc
@ -23,6 +24,7 @@ select -assert-count 1 t:$lut r:LUT=2'b01 r:WIDTH=1 %i %i
select -assert-count 1 t:unknown
select -assert-none t:$lut t:unknown %% t: %D
design -load read
hierarchy -top abc9_test032
proc
@ -38,3 +40,16 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -seq 10 -verify -prove-asserts -show-ports miter
design -reset
read_verilog -icells <<EOT
module abc9_test036(input clk, d, output q);
(* keep *) reg w;
$__ABC9_FF_ ff(.D(d), .Q(w));
wire \ff.clock = clk;
wire \ff.init = 1'b0;
assign q = w;
endmodule
EOT
abc9 -lut 4 -dff