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add testcase for #1614

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Stefan Biereigel 2020-02-03 21:29:54 +01:00
parent b844b078db
commit 90c78f1f85
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tests/various/bug1614.ys Normal file
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read_verilog <<EOT
module testcase;
wire [3:0] #1 a = 4'b0000;
endmodule
EOT