docs: moving code examples

Code now resides in `docs/source/code_examples`.
`CHAPTER_Prog` -> `stubnets`
`APPNOTE_011_Design_Investigation` -> `selections` and `show`
`resources/PRESENTATION_Intro` -> `intro`
`resources/PRESENTATION_ExSyn` -> `synth_flow`
`resources/PRESENTATION_ExAdv` -> `techmap`,  `macc`, and `selections`
`resources/PRESENTATION_ExOth` -> `scrambler` and `axis`

Note that generated images are not yet configured to build from the new code locations.

docs/source/code_examples/.gitignore

@@ -0,0 +1,2 @@
+*.dot
+*.pdf

docs/source/code_examples/axis/axis_master.v

@@ -0,0 +1,27 @@
+module axis_master(aclk, aresetn, tvalid, tready, tdata);
+    input aclk, aresetn, tready;
+    output reg tvalid;
+    output reg [7:0] tdata;
+
+    reg [31:0] state;
+    always @(posedge aclk) begin
+        if (!aresetn) begin
+	    state <= 314159265;
+	    tvalid <= 0;
+	    tdata <= 'bx;
+	end else begin
+	    if (tvalid && tready)
+	    	tvalid <= 0;
+	    if (!tvalid || !tready) begin
+	    //             ^- should not be inverted!
+                state = state ^ state << 13;
+                state = state ^ state >> 7;
+                state = state ^ state << 17;
+		if (state[9:8] == 0) begin
+		    tvalid <= 1;
+		    tdata <= state;
+		end
+	    end
+	end
+    end
+endmodule

docs/source/code_examples/axis/axis_test.v

@@ -0,0 +1,27 @@
+module axis_test(aclk, tready);
+    input aclk, tready;
+    wire aresetn, tvalid;
+    wire [7:0] tdata;
+
+    integer counter = 0;
+    reg aresetn = 0;
+
+    axis_master uut (aclk, aresetn, tvalid, tready, tdata);
+
+    always @(posedge aclk) begin
+    	if (aresetn && tready && tvalid) begin
+	    if (counter == 0) assert(tdata ==  19);
+	    if (counter == 1) assert(tdata ==  99);
+	    if (counter == 2) assert(tdata ==   1);
+	    if (counter == 3) assert(tdata == 244);
+	    if (counter == 4) assert(tdata == 133);
+	    if (counter == 5) assert(tdata == 209);
+	    if (counter == 6) assert(tdata == 241);
+	    if (counter == 7) assert(tdata == 137);
+	    if (counter == 8) assert(tdata == 176);
+	    if (counter == 9) assert(tdata ==   6);
+	    counter <= counter + 1;
+	end
+	aresetn <= 1;
+    end
+endmodule

docs/source/code_examples/axis/axis_test.ys

@@ -0,0 +1,5 @@
+read_verilog -sv axis_master.v axis_test.v
+hierarchy -top axis_test
+
+proc; flatten;;
+sat -seq 50 -prove-asserts

docs/source/code_examples/intro/Makefile

@@ -0,0 +1,13 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: counter_00.dot counter_01.dot counter_02.dot counter_03.dot
+
+counter_00.dot: counter.v counter.ys mycells.lib
+	$(YOSYS) counter_outputs.ys
+
+counter_01.dot: counter_00.dot
+counter_02.dot: counter_00.dot
+counter_03.dot: counter_00.dot
+

docs/source/code_examples/intro/counter.v

@@ -0,0 +1,12 @@
+module counter (clk, rst, en, count);
+
+	input clk, rst, en;
+	output reg [1:0] count;
+
+	always @(posedge clk)
+		if (rst)
+			count <= 2'd0;
+		else if (en)
+			count <= count + 2'd1;
+
+endmodule

docs/source/code_examples/intro/counter.ys

@@ -0,0 +1,21 @@
+# read design
+read_verilog counter.v
+hierarchy -check -top counter
+
+# the high-level stuff
+proc; opt; memory; opt; fsm; opt
+
+# mapping to internal cell library
+techmap; opt
+
+# mapping flip-flops to mycells.lib
+dfflibmap -liberty mycells.lib
+
+# mapping logic to mycells.lib
+abc -liberty mycells.lib
+
+# cleanup
+clean
+
+# write synthesized design
+write_verilog synth.v

docs/source/code_examples/intro/counter_outputs.ys

@@ -0,0 +1,27 @@
+# read design
+read_verilog counter.v
+hierarchy -check -top counter
+
+show -notitle -format dot -prefix counter_00
+
+# the high-level stuff
+proc; opt; memory; opt; fsm; opt
+
+show -notitle -format dot -prefix counter_01
+
+# mapping to internal cell library
+techmap; opt
+
+splitnets -ports;;
+show -notitle -format dot -prefix counter_02
+
+# mapping flip-flops to mycells.lib
+dfflibmap -liberty mycells.lib
+
+# mapping logic to mycells.lib
+abc -liberty mycells.lib
+
+# cleanup
+clean
+
+show -notitle -lib mycells.v -format dot -prefix counter_03

docs/source/code_examples/intro/mycells.lib

@@ -0,0 +1,38 @@
+library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NOT) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(NAND) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+}

docs/source/code_examples/intro/mycells.v

@@ -0,0 +1,23 @@
+
+module NOT(A, Y);
+input A;
+output Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+	Q <= D;
+endmodule
+

docs/source/code_examples/macc/Makefile

@@ -0,0 +1,12 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: macc_simple_xmap.pdf macc_xilinx_xmap.pdf
+
+macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+	$(YOSYS) macc_simple_test.ys
+
+macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
+	$(YOSYS) macc_xilinx_test.ys
+

docs/source/code_examples/macc/macc_simple_test.v

@@ -0,0 +1,6 @@
+module test(a, b, c, d, y);
+input [15:0] a, b;
+input [31:0] c, d;
+output [31:0] y;
+assign y = a * b + c + d;
+endmodule

docs/source/code_examples/macc/macc_simple_test.ys

@@ -0,0 +1,37 @@
+read_verilog macc_simple_test.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -constports -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_test_01.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_test_02.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_xmap.v
+hierarchy -check -top macc_16_16_32;;
+
+show -prefix macc_simple_xmap -format pdf -notitle

docs/source/code_examples/macc/macc_simple_test_01.v

@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + c*d + x;
+endmodule

docs/source/code_examples/macc/macc_simple_test_02.v

@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + (c*d + x);
+endmodule

docs/source/code_examples/macc/macc_simple_xmap.v

@@ -0,0 +1,6 @@
+module macc_16_16_32(a, b, c, y);
+input [15:0] a, b;
+input [31:0] c;
+output [31:0] y;
+assign y = a*b + c;
+endmodule

docs/source/code_examples/macc/macc_xilinx_swap_map.v

@@ -0,0 +1,28 @@
+(* techmap_celltype = "$mul" *)
+module mul_swap_ports (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire _TECHMAP_FAIL_ = A_WIDTH <= B_WIDTH;
+
+\$mul #(
+	.A_SIGNED(B_SIGNED),
+	.B_SIGNED(A_SIGNED),
+	.A_WIDTH(B_WIDTH),
+	.B_WIDTH(A_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(B),
+	.B(A),
+	.Y(Y)
+);
+
+endmodule

docs/source/code_examples/macc/macc_xilinx_test.v

@@ -0,0 +1,13 @@
+module test1(a, b, c, d, e, f, y);
+    input [19:0] a, b, c;
+    input [15:0] d, e, f;
+    output [41:0] y;
+    assign y = a*b + c*d + e*f;
+endmodule
+
+module test2(a, b, c, d, e, f, y);
+    input [19:0] a, b, c;
+    input [15:0] d, e, f;
+    output [41:0] y;
+    assign y = a*b + (c*d + e*f);
+endmodule

docs/source/code_examples/macc/macc_xilinx_test.ys

@@ -0,0 +1,43 @@
+read_verilog macc_xilinx_test.v
+read_verilog -lib -icells macc_xilinx_unwrap_map.v
+read_verilog -lib -icells macc_xilinx_xmap.v
+hierarchy -check ;;
+
+show -prefix macc_xilinx_test1a -format pdf -notitle test1
+show -prefix macc_xilinx_test2a -format pdf -notitle test2
+
+techmap -map macc_xilinx_swap_map.v;;
+
+show -prefix macc_xilinx_test1b -format pdf -notitle test1
+show -prefix macc_xilinx_test2b -format pdf -notitle test2
+
+techmap -map macc_xilinx_wrap_map.v
+
+connwrappers -unsigned $__mul_wrapper Y Y_WIDTH \
+             -unsigned $__add_wrapper Y Y_WIDTH;;
+
+show -prefix macc_xilinx_test1c -format pdf -notitle test1
+show -prefix macc_xilinx_test2c -format pdf -notitle test2
+
+design -push
+read_verilog macc_xilinx_xmap.v
+techmap -map macc_xilinx_swap_map.v
+techmap -map macc_xilinx_wrap_map.v;;
+design -save __macc_xilinx_xmap
+design -pop
+
+extract -constports -ignore_parameters \
+        -map %__macc_xilinx_xmap       \
+        -swap $__add_wrapper A,B ;;
+
+show -prefix macc_xilinx_test1d -format pdf -notitle test1
+show -prefix macc_xilinx_test2d -format pdf -notitle test2
+
+techmap -map macc_xilinx_unwrap_map.v;;
+
+show -prefix macc_xilinx_test1e -format pdf -notitle test1
+show -prefix macc_xilinx_test2e -format pdf -notitle test2
+
+design -load __macc_xilinx_xmap
+show -prefix macc_xilinx_xmap -format pdf -notitle
+

docs/source/code_examples/macc/macc_xilinx_unwrap_map.v

@@ -0,0 +1,61 @@
+module \$__mul_wrapper (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [17:0] A;
+input [24:0] B;
+output [47:0] Y;
+
+wire [A_WIDTH-1:0] A_ORIG = A;
+wire [B_WIDTH-1:0] B_ORIG = B;
+wire [Y_WIDTH-1:0] Y_ORIG;
+assign Y = Y_ORIG;
+
+\$mul #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_ORIG),
+	.B(B_ORIG),
+	.Y(Y_ORIG)
+);
+
+endmodule
+
+module \$__add_wrapper (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [47:0] A;
+input [47:0] B;
+output [47:0] Y;
+
+wire [A_WIDTH-1:0] A_ORIG = A;
+wire [B_WIDTH-1:0] B_ORIG = B;
+wire [Y_WIDTH-1:0] Y_ORIG;
+assign Y = Y_ORIG;
+
+\$add #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_ORIG),
+	.B(B_ORIG),
+	.Y(Y_ORIG)
+);
+
+endmodule

docs/source/code_examples/macc/macc_xilinx_wrap_map.v

@@ -0,0 +1,89 @@
+(* techmap_celltype = "$mul" *)
+module mul_wrap (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [17:0] A_18 = A;
+wire [24:0] B_25 = B;
+wire [47:0] Y_48;
+assign Y = Y_48;
+
+wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+reg _TECHMAP_FAIL_;
+initial begin
+	_TECHMAP_FAIL_ <= 0;
+	if (A_SIGNED || B_SIGNED)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH < 4 || B_WIDTH < 4)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH > 18 || B_WIDTH > 25)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH*B_WIDTH < 100)
+		_TECHMAP_FAIL_ <= 1;
+end
+
+\$__mul_wrapper #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_18),
+	.B(B_25),
+	.Y(Y_48)
+);
+
+endmodule
+
+(* techmap_celltype = "$add" *)
+module add_wrap (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+wire [47:0] A_48 = A;
+wire [47:0] B_48 = B;
+wire [47:0] Y_48;
+assign Y = Y_48;
+
+wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+reg _TECHMAP_FAIL_;
+initial begin
+	_TECHMAP_FAIL_ <= 0;
+	if (A_SIGNED || B_SIGNED)
+		_TECHMAP_FAIL_ <= 1;
+	if (A_WIDTH < 10 && B_WIDTH < 10)
+		_TECHMAP_FAIL_ <= 1;
+end
+
+\$__add_wrapper #(
+	.A_SIGNED(A_SIGNED),
+	.B_SIGNED(B_SIGNED),
+	.A_WIDTH(A_WIDTH),
+	.B_WIDTH(B_WIDTH),
+	.Y_WIDTH(Y_WIDTH)
+) _TECHMAP_REPLACE_ (
+	.A(A_48),
+	.B(B_48),
+	.Y(Y_48)
+);
+
+endmodule

docs/source/code_examples/macc/macc_xilinx_xmap.v

@@ -0,0 +1,10 @@
+module DSP48_MACC (a, b, c, y);
+
+input [17:0] a;
+input [24:0] b;
+input [47:0] c;
+output [47:0] y;
+
+assign y = a*b + c;
+
+endmodule

docs/source/code_examples/primetest.v

@@ -0,0 +1,4 @@
+module primetest(p, a, b, ok);
+input [15:0] p, a, b;
+output ok = p != a*b || a == 1 || b == 1;
+endmodule

docs/source/code_examples/scrambler/Makefile

@@ -0,0 +1,8 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: scrambler_p01.dot scrambler_p02.dot
+
+scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v
+	$(YOSYS) scrambler.ys

docs/source/code_examples/scrambler/scrambler.v

@@ -0,0 +1,14 @@
+module scrambler(
+        input clk, rst, in_bit,
+        output reg out_bit
+);
+    reg [31:0] xs;
+    always @(posedge clk) begin
+    	if (rst)
+	    xs = 1;
+        xs = xs ^ (xs << 13);
+        xs = xs ^ (xs >> 17);
+        xs = xs ^ (xs << 5);
+        out_bit <= in_bit ^ xs[0];
+    end
+endmodule

docs/source/code_examples/scrambler/scrambler.ys

@@ -0,0 +1,22 @@
+read_verilog scrambler.v
+
+hierarchy; proc;;
+
+cd scrambler
+submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
+cd ..
+
+show -prefix scrambler_p01 -format dot -notitle scrambler
+show -prefix scrambler_p02 -format dot -notitle xorshift32
+
+echo on
+
+cd xorshift32
+rename n2 in
+rename n1 out
+
+eval -set in 1 -show out
+eval -set in 270369 -show out
+
+sat -set out 632435482
+

docs/source/code_examples/selections/Makefile

@@ -0,0 +1,32 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+SUMPROD = sumprod_00 sumprod_01 sumprod_02 sumprod_03 sumprod_04 sumprod_05
+SUMPROD_DOTS := $(addsuffix .dot,$(SUMPROD))
+
+MEMDEMO = memdemo_00 memdemo_01
+MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO))
+
+SUBMOD = submod_00 submod_01 submod_02 submod_03
+SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD))
+
+all: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS)
+
+select.dot: select.v select.ys
+	$(YOSYS) select.ys
+
+$(SUMPROD_DOTS): sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
+
+$(MEMDEMO_DOTS): memdemo.v
+	$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
+	$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
+
+$(SUBMOD_DOTS): submod.ys memdemo.v
+	$(YOSYS) submod.ys

docs/source/code_examples/selections/foobaraddsub.v

@@ -0,0 +1,8 @@
+module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
+  input [7:0] a, b, c, d;
+  output [7:0] fa, fs, ba, bs;
+  assign fa = a + (* foo *) b;
+  assign fs = a - (* foo *) b;
+  assign ba = c + (* bar *) d;
+  assign bs = c - (* bar *) d;
+endmodule

docs/source/code_examples/selections/memdemo.v

@@ -0,0 +1,19 @@
+module memdemo(clk, d, y);
+
+input clk;
+input [3:0] d;
+output reg [3:0] y;
+
+integer i;
+reg [1:0] s1, s2;
+reg [3:0] mem [0:3];
+
+always @(posedge clk) begin
+    for (i = 0; i < 4; i = i+1)
+        mem[i] <= mem[(i+1) % 4] + mem[(i+2) % 4];
+    { s2, s1 } = d ? { s1, s2 } ^ d : 4'b0;
+    mem[s1] <= d;
+    y <= mem[s2];
+end
+
+endmodule

docs/source/code_examples/selections/select.v

@@ -0,0 +1,15 @@
+module test(clk, s, a, y);
+    input clk, s;
+    input [15:0] a;
+    output [15:0] y;
+    reg [15:0] b, c;
+
+    always @(posedge clk) begin
+        b <= a;
+        c <= b;
+    end
+
+    wire [15:0] state_a = (a ^ b) + c;
+    wire [15:0] state_b = (a ^ b) - c;
+    assign y = !s ? state_a : state_b;
+endmodule

docs/source/code_examples/selections/select.ys

@@ -0,0 +1,10 @@
+read_verilog select.v
+hierarchy -check -top test
+proc; opt
+cd test
+select -set cone_a state_a %ci*:-$dff
+select -set cone_b state_b %ci*:-$dff
+select -set cone_ab @cone_a @cone_b %i
+show -prefix select -format dot -notitle \
+     -color red @cone_ab -color magenta @cone_a \
+     -color blue @cone_b

docs/source/code_examples/selections/submod.ys

@@ -0,0 +1,16 @@
+read_verilog memdemo.v
+proc; opt; memory; opt
+
+cd memdemo
+select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
+select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
+select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
+submod -name scramble @scramble
+submod -name outstage @outstage
+submod -name selstage @selstage
+
+cd ..
+show -format dot -prefix submod_00 memdemo
+show -format dot -prefix submod_01 scramble
+show -format dot -prefix submod_02 outstage
+show -format dot -prefix submod_03 selstage

docs/source/code_examples/selections/sumprod.v

@@ -0,0 +1,12 @@
+module sumprod(a, b, c, sum, prod);
+
+  input [7:0] a, b, c;
+  output [7:0] sum, prod;
+
+  {* sumstuff *}
+  assign sum = a + b + c;
+  {* *}
+
+  assign prod = a * b * c;
+
+endmodule

docs/source/code_examples/show/Makefile

@@ -0,0 +1,23 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+EXAMPLE = example_00 example_01 example_02 example_03
+EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
+
+CMOS = cmos_00 cmos_01
+CMOS_DOTS := $(addsuffix .dot,$(CMOS))
+
+all: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
+
+splice.dot: splice.v
+	$(YOSYS) -p 'proc; opt; show -format dot -prefix splice' splice.v
+
+$(EXAMPLE_DOTS): example.v example.ys
+	$(YOSYS) example.ys
+
+cmos_00.dot: cmos.v
+	$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
+
+cmos_01.dot: cmos.v
+	$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'

docs/source/code_examples/show/cmos.v

@@ -0,0 +1,3 @@
+module cmos_demo(input a, b, output [1:0] y);
+assign y = a + b;
+endmodule

docs/source/code_examples/show/example.v

@@ -0,0 +1,6 @@
+module example(input clk, a, b, c,
+               output reg [1:0] y);
+    always @(posedge clk)
+        if (c)
+            y <= c ? a + b : 2'd0;
+endmodule

docs/source/code_examples/show/example.ys

@@ -0,0 +1,11 @@
+read_verilog example.v
+show -format dot -prefix example_00
+proc
+show -format dot -prefix example_01
+opt
+show -format dot -prefix example_02
+
+cd example
+select t:$add
+show -format dot -prefix example_03
+

docs/source/code_examples/show/splice.v

@@ -0,0 +1,10 @@
+module splice_demo(a, b, c, d, e, f, x, y);
+
+input [1:0] a, b, c, d, e, f;
+output [1:0] x = {a[0], a[1]};
+
+output [11:0] y;
+assign {y[11:4], y[1:0], y[3:2]} =
+                {a, b, -{c, d}, ~{e, f}};
+
+endmodule

docs/source/code_examples/stubnets/.gitignore

@@ -0,0 +1,3 @@
+stubnets.so
+stubnets.d
+*.log

docs/source/code_examples/stubnets/Makefile

@@ -0,0 +1,12 @@
+test: stubnets.so
+	yosys -ql test1.log -m ./stubnets.so test.v -p "stubnets"
+	yosys -ql test2.log -m ./stubnets.so test.v -p "opt; stubnets"
+	yosys -ql test3.log -m ./stubnets.so test.v -p "techmap; opt; stubnets -report_bits"
+	tail test1.log test2.log test3.log
+
+stubnets.so: stubnets.cc
+	yosys-config --exec --cxx --cxxflags --ldflags -o $@ -shared $^ --ldlibs
+
+clean:
+	rm -f test1.log test2.log test3.log
+	rm -f stubnets.so stubnets.d

docs/source/code_examples/stubnets/stubnets.cc

@@ -0,0 +1,130 @@
+// This is free and unencumbered software released into the public domain.
+//
+// Anyone is free to copy, modify, publish, use, compile, sell, or
+// distribute this software, either in source code form or as a compiled
+// binary, for any purpose, commercial or non-commercial, and by any
+// means.
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+#include <string>
+#include <map>
+#include <set>
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+// this function is called for each module in the design
+static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool report_bits)
+{
+	// use a SigMap to convert nets to a unique representation
+	SigMap sigmap(module);
+
+	// count how many times a single-bit signal is used
+	std::map<RTLIL::SigBit, int> bit_usage_count;
+
+	// count output lines for this module (needed only for summary output at the end)
+	int line_count = 0;
+
+	log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));
+
+	// For all ports on all cells
+	for (auto &cell_iter : module->cells_)
+	for (auto &conn : cell_iter.second->connections())
+	{
+		// Get the signals on the port
+		// (use sigmap to get a uniqe signal name)
+		RTLIL::SigSpec sig = sigmap(conn.second);
+
+		// add each bit to bit_usage_count, unless it is a constant
+		for (auto &bit : sig)
+			if (bit.wire != NULL)
+				bit_usage_count[bit]++;
+	}
+
+	// for each wire in the module
+	for (auto &wire_iter : module->wires_)
+	{
+		RTLIL::Wire *wire = wire_iter.second;
+
+		// .. but only selected wires
+		if (!design->selected(module, wire))
+			continue;
+
+		// add +1 usage if this wire actually is a port
+		int usage_offset = wire->port_id > 0 ? 1 : 0;
+
+		// we will record which bits of the (possibly multi-bit) wire are stub signals
+		std::set<int> stub_bits;
+
+		// get a signal description for this wire and split it into separate bits
+		RTLIL::SigSpec sig = sigmap(wire);
+
+		// for each bit (unless it is a constant):
+		// check if it is used at least two times and add to stub_bits otherwise
+		for (int i = 0; i < GetSize(sig); i++)
+			if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
+				stub_bits.insert(i);
+
+		// continue if no stub bits found
+		if (stub_bits.size() == 0)
+			continue;
+
+		// report stub bits and/or stub wires, don't report single bits
+		// if called with report_bits set to false.
+		if (GetSize(stub_bits) == GetSize(sig)) {
+			log("  found stub wire: %s\n", RTLIL::id2cstr(wire->name));
+		} else {
+			if (!report_bits)
+				continue;
+			log("  found wire with stub bits: %s [", RTLIL::id2cstr(wire->name));
+			for (int bit : stub_bits)
+				log("%s%d", bit == *stub_bits.begin() ? "" : ", ", bit);
+			log("]\n");
+		}
+
+		// we have outputted a line, increment summary counter
+		line_count++;
+	}
+
+	// report summary
+	if (report_bits)
+		log("  found %d stub wires or wires with stub bits.\n", line_count);
+	else
+		log("  found %d stub wires.\n", line_count);
+}
+
+// each pass contains a singleton object that is derived from Pass
+struct StubnetsPass : public Pass {
+	StubnetsPass() : Pass("stubnets") { }
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		// variables to mirror information from passed options
+		bool report_bits = 0;
+
+		log_header(design, "Executing STUBNETS pass (find stub nets).\n");
+
+		// parse options
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			std::string arg = args[argidx];
+			if (arg == "-report_bits") {
+				report_bits = true;
+				continue;
+			}
+			break;
+		}
+
+		// handle extra options (e.g. selection)
+		extra_args(args, argidx, design);
+
+		// call find_stub_nets() for each module that is either
+		// selected as a whole or contains selected objects.
+		for (auto &it : design->modules_)
+			if (design->selected_module(it.first))
+				find_stub_nets(design, it.second, report_bits);
+	}
+} StubnetsPass;
+
+PRIVATE_NAMESPACE_END

docs/source/code_examples/stubnets/test.v

@@ -0,0 +1,8 @@
+module uut(in1, in2, in3, out1, out2);
+
+input [8:0] in1, in2, in3;
+output [8:0] out1, out2;
+
+assign out1 = in1 + in2 + (in3 >> 4);
+
+endmodule

docs/source/code_examples/synth_flow/Makefile

@@ -0,0 +1,24 @@
+
+TARGETS += proc_01 proc_02 proc_03
+TARGETS += opt_01 opt_02 opt_03 opt_04
+TARGETS += memory_01 memory_02
+TARGETS += techmap_01
+TARGETS += abc_01
+
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: $(addsuffix .pdf,$(TARGETS))
+
+define make_pdf_template
+$(1).pdf: $(1)*.v $(1)*.ys
+	$(YOSYS) -p 'script $(1).ys; show -notitle -prefix $(1) -format pdf'
+endef
+
+$(foreach trg,$(TARGETS),$(eval $(call make_pdf_template,$(trg))))
+
+clean:
+	rm -f $(addsuffix .pdf,$(TARGETS))
+	rm -f $(addsuffix .dot,$(TARGETS))
+

docs/source/code_examples/synth_flow/abc_01.v

@@ -0,0 +1,10 @@
+module test(input clk, a, b, c,
+            output reg y);
+
+	reg [2:0] q1, q2;
+	always @(posedge clk) begin
+		q1 <= { a, b, c };
+		q2 <= q1;
+		y <= ^q2;
+	end
+endmodule

docs/source/code_examples/synth_flow/abc_01.ys

@@ -0,0 +1,5 @@
+read_verilog abc_01.v
+read_verilog -lib abc_01_cells.v
+hierarchy -check -top test
+proc; opt; techmap
+abc -dff -liberty abc_01_cells.lib;;

docs/source/code_examples/synth_flow/abc_01_cells.lib

@@ -0,0 +1,54 @@
+// test comment
+/* test comment */
+library(demo) {
+  cell(BUF) {
+    area: 6;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A"; }
+  }
+  cell(NOT) {
+    area: 3;
+    pin(A) { direction: input; }
+    pin(Y) { direction: output;
+              function: "A'"; }
+  }
+  cell(NAND) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A*B)'"; }
+  }
+  cell(NOR) {
+    area: 4;
+    pin(A) { direction: input; }
+    pin(B) { direction: input; }
+    pin(Y) { direction: output;
+             function: "(A+B)'"; }
+  }
+  cell(DFF) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+  }
+  cell(DFFSR) {
+    area: 18;
+    ff(IQ, IQN) { clocked_on: C;
+                  next_state: D;
+                      preset: S;
+                       clear: R; }
+    pin(C) { direction: input;
+                 clock: true; }
+    pin(D) { direction: input; }
+    pin(Q) { direction: output;
+              function: "IQ"; }
+    pin(S) { direction: input; }
+    pin(R) { direction: input; }
+  }
+}

docs/source/code_examples/synth_flow/abc_01_cells.v

@@ -0,0 +1,40 @@
+
+module BUF(A, Y);
+input A;
+output Y = A;
+endmodule
+
+module NOT(A, Y);
+input A;
+output Y = ~A;
+endmodule
+
+module NAND(A, B, Y);
+input A, B;
+output Y = ~(A & B);
+endmodule
+
+module NOR(A, B, Y);
+input A, B;
+output Y = ~(A | B);
+endmodule
+
+module DFF(C, D, Q);
+input C, D;
+output reg Q;
+always @(posedge C)
+	Q <= D;
+endmodule
+
+module DFFSR(C, D, Q, S, R);
+input C, D, S, R;
+output reg Q;
+always @(posedge C, posedge S, posedge R)
+	if (S)
+		Q <= 1'b1;
+	else if (R)
+		Q <= 1'b0;
+	else
+		Q <= D;
+endmodule
+

docs/source/code_examples/synth_flow/memory_01.v

@@ -0,0 +1,9 @@
+module test(input      CLK, ADDR,
+            input      [7:0] DIN,
+	    output reg [7:0] DOUT);
+    reg [7:0] mem [0:1];
+    always @(posedge CLK) begin
+        mem[ADDR] <= DIN;
+	DOUT <= mem[ADDR];
+    end
+endmodule

docs/source/code_examples/synth_flow/memory_01.ys

@@ -0,0 +1,3 @@
+read_verilog memory_01.v
+hierarchy -check -top test
+proc;; memory; opt

docs/source/code_examples/synth_flow/memory_02.v

@@ -0,0 +1,27 @@
+module test(
+    input             WR1_CLK,  WR2_CLK,
+    input             WR1_WEN,  WR2_WEN,
+    input      [7:0]  WR1_ADDR, WR2_ADDR,
+    input      [7:0]  WR1_DATA, WR2_DATA,
+    input             RD1_CLK,  RD2_CLK,
+    input      [7:0]  RD1_ADDR, RD2_ADDR,
+    output reg [7:0]  RD1_DATA, RD2_DATA
+);
+
+reg [7:0] memory [0:255];
+
+always @(posedge WR1_CLK)
+    if (WR1_WEN)
+        memory[WR1_ADDR] <= WR1_DATA;
+
+always @(posedge WR2_CLK)
+    if (WR2_WEN)
+        memory[WR2_ADDR] <= WR2_DATA;
+
+always @(posedge RD1_CLK)
+    RD1_DATA <= memory[RD1_ADDR];
+
+always @(posedge RD2_CLK)
+    RD2_DATA <= memory[RD2_ADDR];
+
+endmodule

docs/source/code_examples/synth_flow/memory_02.ys

@@ -0,0 +1,4 @@
+read_verilog memory_02.v
+hierarchy -check -top test
+proc;; memory -nomap
+opt -mux_undef -mux_bool

docs/source/code_examples/synth_flow/opt_01.v

@@ -0,0 +1,3 @@
+module test(input A, B, output Y);
+assign Y = A ? A ? B : 1'b1 : B;
+endmodule

docs/source/code_examples/synth_flow/opt_01.ys

@@ -0,0 +1,3 @@
+read_verilog opt_01.v
+hierarchy -check -top test
+opt

docs/source/code_examples/synth_flow/opt_02.v

@@ -0,0 +1,3 @@
+module test(input A, output Y, Z);
+assign Y = A == A, Z = A != A;
+endmodule

docs/source/code_examples/synth_flow/opt_02.ys

@@ -0,0 +1,3 @@
+read_verilog opt_02.v
+hierarchy -check -top test
+opt

docs/source/code_examples/synth_flow/opt_03.v

@@ -0,0 +1,4 @@
+module test(input  [3:0] A, B,
+            output [3:0] Y, Z);
+assign Y = A + B, Z = B + A;
+endmodule

docs/source/code_examples/synth_flow/opt_03.ys

@@ -0,0 +1,3 @@
+read_verilog opt_03.v
+hierarchy -check -top test
+opt

docs/source/code_examples/synth_flow/opt_04.v

@@ -0,0 +1,19 @@
+module test(input CLK, ARST,
+            output [7:0] Q1, Q2, Q3);
+
+wire NO_CLK = 0;
+
+always @(posedge CLK, posedge ARST)
+	if (ARST)
+		Q1 <= 42;
+
+always @(posedge NO_CLK, posedge ARST)
+	if (ARST)
+		Q2 <= 42;
+	else
+		Q2 <= 23;
+
+always @(posedge CLK)
+	Q3 <= 42;
+
+endmodule

docs/source/code_examples/synth_flow/opt_04.ys

@@ -0,0 +1,3 @@
+read_verilog opt_04.v
+hierarchy -check -top test
+proc; opt

docs/source/code_examples/synth_flow/proc_01.v

@@ -0,0 +1,7 @@
+module test(input D, C, R, output reg Q);
+    always @(posedge C, posedge R)
+        if (R)
+	    Q <= 0;
+	else
+	    Q <= D;
+endmodule

docs/source/code_examples/synth_flow/proc_01.ys

@@ -0,0 +1,3 @@
+read_verilog proc_01.v
+hierarchy -check -top test
+proc;;

docs/source/code_examples/synth_flow/proc_02.v

@@ -0,0 +1,8 @@
+module test(input D, C, R, RV,
+            output reg Q);
+    always @(posedge C, posedge R)
+        if (R)
+	    Q <= RV;
+	else
+	    Q <= D;
+endmodule

docs/source/code_examples/synth_flow/proc_02.ys

@@ -0,0 +1,3 @@
+read_verilog proc_02.v
+hierarchy -check -top test
+proc;;

docs/source/code_examples/synth_flow/proc_03.v

@@ -0,0 +1,10 @@
+module test(input A, B, C, D, E,
+            output reg Y);
+    always @* begin
+	Y <= A;
+	if (B)
+	    Y <= C;
+	if (D)
+	    Y <= E;
+    end
+endmodule

docs/source/code_examples/synth_flow/proc_03.ys

@@ -0,0 +1,3 @@
+read_verilog proc_03.v
+hierarchy -check -top test
+proc;;

docs/source/code_examples/synth_flow/techmap_01.v

@@ -0,0 +1,4 @@
+module test(input [31:0]  a, b,
+            output [31:0] y);
+assign y = a + b;
+endmodule

docs/source/code_examples/synth_flow/techmap_01.ys

@@ -0,0 +1,3 @@
+read_verilog techmap_01.v
+hierarchy -check -top test
+techmap -map techmap_01_map.v;;

docs/source/code_examples/synth_flow/techmap_01_map.v

@@ -0,0 +1,24 @@
+module \$add (A, B, Y);
+
+parameter A_SIGNED = 0;
+parameter B_SIGNED = 0;
+parameter A_WIDTH = 1;
+parameter B_WIDTH = 1;
+parameter Y_WIDTH = 1;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [Y_WIDTH-1:0] Y;
+
+generate
+  if ((A_WIDTH == 32) && (B_WIDTH == 32))
+    begin
+      wire [16:0] S1 = A[15:0] + B[15:0];
+      wire [15:0] S2 = A[31:16] + B[31:16] + S1[16];
+      assign Y = {S2[15:0], S1[15:0]};
+    end
+  else
+    wire _TECHMAP_FAIL_ = 1;
+endgenerate
+
+endmodule

docs/source/code_examples/techmap/Makefile

@@ -0,0 +1,21 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot
+
+red_or3x1.dot: red_or3x1_*
+	$(YOSYS) red_or3x1_test.ys
+
+sym_mul.dot: sym_mul_*
+	$(YOSYS) sym_mul_test.ys
+
+mymul.dot: mymul_*
+	$(YOSYS) mymul_test.ys
+
+mulshift.dot: mulshift_*
+	$(YOSYS) mulshift_test.ys
+
+addshift.dot: addshift_*
+	$(YOSYS) addshift_test.ys
+

docs/source/code_examples/techmap/addshift_map.v

@@ -0,0 +1,20 @@
+module \$add (A, B, Y);
+  parameter A_SIGNED = 0;
+  parameter B_SIGNED = 0;
+  parameter A_WIDTH = 1;
+  parameter B_WIDTH = 1;
+  parameter Y_WIDTH = 1;
+
+  input [A_WIDTH-1:0] A;
+  input [B_WIDTH-1:0] B;
+  output [Y_WIDTH-1:0] Y;
+
+  parameter _TECHMAP_BITS_CONNMAP_ = 0;
+  parameter _TECHMAP_CONNMAP_A_ = 0;
+  parameter _TECHMAP_CONNMAP_B_ = 0;
+
+  wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
+                        _TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
+
+  assign Y = A << 1;
+endmodule

docs/source/code_examples/techmap/addshift_test.v

@@ -0,0 +1,5 @@
+module test (A, B, X, Y);
+input [7:0] A, B;
+output [7:0] X = A + B;
+output [7:0] Y = A + A;
+endmodule

docs/source/code_examples/techmap/addshift_test.ys

@@ -0,0 +1,6 @@
+read_verilog addshift_test.v
+hierarchy -check -top test
+
+techmap -map addshift_map.v;;
+
+show -prefix addshift -format dot -notitle

docs/source/code_examples/techmap/mulshift_map.v

@@ -0,0 +1,26 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output reg [WIDTH-1:0] Y;
+
+    parameter _TECHMAP_CONSTVAL_A_ = WIDTH'bx;
+    parameter _TECHMAP_CONSTVAL_B_ = WIDTH'bx;
+
+    reg _TECHMAP_FAIL_;
+    wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+    integer i;
+    always @* begin
+    	_TECHMAP_FAIL_ <= 1;
+        for (i = 0; i < WIDTH; i=i+1) begin
+            if (_TECHMAP_CONSTVAL_A_ === WIDTH'd1 << i) begin
+	        _TECHMAP_FAIL_ <= 0;
+                Y <= B << i;
+	    end
+            if (_TECHMAP_CONSTVAL_B_ === WIDTH'd1 << i) begin
+	        _TECHMAP_FAIL_ <= 0;
+                Y <= A << i;
+	    end
+	end
+    end
+endmodule

docs/source/code_examples/techmap/mulshift_test.v

@@ -0,0 +1,5 @@
+module test (A, X, Y);
+input [7:0] A;
+output [7:0] X = A * 8'd 6;
+output [7:0] Y = A * 8'd 8;
+endmodule

docs/source/code_examples/techmap/mulshift_test.ys

@@ -0,0 +1,7 @@
+read_verilog mulshift_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+        -map mulshift_map.v;;
+
+show -prefix mulshift -format dot -notitle -lib sym_mul_cells.v

docs/source/code_examples/techmap/mymul_map.v

@@ -0,0 +1,15 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output reg [WIDTH-1:0] Y;
+
+    wire [1023:0] _TECHMAP_DO_ = "proc; clean";
+
+    integer i;
+    always @* begin
+        Y = 0;
+        for (i = 0; i < WIDTH; i=i+1)
+            if (A[i])
+                Y = Y + (B << i);
+    end
+endmodule

docs/source/code_examples/techmap/mymul_test.v

@@ -0,0 +1,4 @@
+module test(A, B, Y);
+    input  [1:0] A, B;
+    output [1:0] Y = A * B;
+endmodule

docs/source/code_examples/techmap/mymul_test.ys

@@ -0,0 +1,15 @@
+read_verilog mymul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v \
+        -map mymul_map.v;;
+
+rename test test_mapped
+read_verilog mymul_test.v
+miter -equiv test test_mapped miter
+flatten miter
+
+sat -verify -prove trigger 0 miter
+
+splitnets -ports test_mapped/A
+show -prefix mymul -format dot -notitle test_mapped

docs/source/code_examples/techmap/red_or3x1_cells.v

@@ -0,0 +1,5 @@
+module OR3X1(A, B, C, Y);
+    input A, B, C;
+    output Y;
+    assign Y = A | B | C;
+endmodule

docs/source/code_examples/techmap/red_or3x1_map.v

@@ -0,0 +1,48 @@
+module \$reduce_or (A, Y);
+
+    parameter A_SIGNED = 0;
+    parameter A_WIDTH = 0;
+    parameter Y_WIDTH = 0;
+
+    input [A_WIDTH-1:0] A;
+    output [Y_WIDTH-1:0] Y;
+
+    function integer min;
+        input integer a, b;
+        begin
+            if (a < b)
+                min = a;
+            else
+                min = b;
+        end
+    endfunction
+
+    genvar i;
+    generate begin
+        if (A_WIDTH == 0) begin
+            assign Y = 0;
+        end
+        if (A_WIDTH == 1) begin
+            assign Y = A;
+        end
+        if (A_WIDTH == 2) begin
+            wire ybuf;
+            OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
+            assign Y = ybuf;
+        end
+        if (A_WIDTH == 3) begin
+            wire ybuf;
+            OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
+            assign Y = ybuf;
+        end
+        if (A_WIDTH > 3) begin
+            localparam next_stage_sz = (A_WIDTH+2) / 3;
+            wire [next_stage_sz-1:0] next_stage;
+            for (i = 0; i < next_stage_sz; i = i+1) begin
+                localparam bits = min(A_WIDTH - 3*i, 3);
+                assign next_stage[i] = |A[3*i +: bits];
+            end
+            assign Y = |next_stage;
+        end
+    end endgenerate
+endmodule

docs/source/code_examples/techmap/red_or3x1_test.v

@@ -0,0 +1,5 @@
+module test (A, Y);
+    input [6:0] A;
+    output Y;
+    assign Y = |A;
+endmodule

docs/source/code_examples/techmap/red_or3x1_test.ys

@@ -0,0 +1,7 @@
+read_verilog red_or3x1_test.v
+hierarchy -check -top test
+
+techmap -map red_or3x1_map.v;;
+
+splitnets -ports
+show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v

docs/source/code_examples/techmap/sym_mul_cells.v

@@ -0,0 +1,6 @@
+module MYMUL(A, B, Y);
+    parameter WIDTH = 1;
+    input [WIDTH-1:0] A, B;
+    output [WIDTH-1:0] Y;
+    assign Y = A * B;
+endmodule

docs/source/code_examples/techmap/sym_mul_map.v

@@ -0,0 +1,15 @@
+module \$mul (A, B, Y);
+    parameter A_SIGNED = 0;
+    parameter B_SIGNED = 0;
+    parameter A_WIDTH = 1;
+    parameter B_WIDTH = 1;
+    parameter Y_WIDTH = 1;
+
+    input [A_WIDTH-1:0] A;
+    input [B_WIDTH-1:0] B;
+    output [Y_WIDTH-1:0] Y;
+
+    wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH;
+
+    MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) );
+endmodule

docs/source/code_examples/techmap/sym_mul_test.v

@@ -0,0 +1,5 @@
+module test(A, B, C, Y1, Y2);
+    input   [7:0] A, B, C;
+    output  [7:0] Y1 = A * B;
+    output [15:0] Y2 = A * C;
+endmodule

docs/source/code_examples/techmap/sym_mul_test.ys

@@ -0,0 +1,6 @@
+read_verilog sym_mul_test.v
+hierarchy -check -top test
+
+techmap -map sym_mul_map.v;;
+
+show -prefix sym_mul -format dot -notitle -lib sym_mul_cells.v