diff --git a/docs/resources/PRESENTATION_ExAdv/Makefile b/docs/resources/PRESENTATION_ExAdv/Makefile
deleted file mode 100644
index fc6ba6902..000000000
--- a/docs/resources/PRESENTATION_ExAdv/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-PROGRAM_PREFIX :=
-
-YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
-
-all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
-		macc_simple_xmap.pdf macc_xilinx_xmap.pdf
-
-select.pdf: select.v select.ys
-	$(YOSYS) select.ys
-
-red_or3x1.pdf: red_or3x1_*
-	$(YOSYS) red_or3x1_test.ys
-
-sym_mul.pdf: sym_mul_*
-	$(YOSYS) sym_mul_test.ys
-
-mymul.pdf: mymul_*
-	$(YOSYS) mymul_test.ys
-
-mulshift.pdf: mulshift_*
-	$(YOSYS) mulshift_test.ys
-
-addshift.pdf: addshift_*
-	$(YOSYS) addshift_test.ys
-
-macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
-	$(YOSYS) macc_simple_test.ys
-
-macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
-	$(YOSYS) macc_xilinx_test.ys
-
diff --git a/docs/resources/PRESENTATION_ExOth/.gitignore b/docs/resources/PRESENTATION_ExOth/.gitignore
deleted file mode 100644
index 3af2b8451..000000000
--- a/docs/resources/PRESENTATION_ExOth/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-*.dot
-*.pdf
-*.log
diff --git a/docs/resources/PRESENTATION_ExOth/Makefile b/docs/resources/PRESENTATION_ExOth/Makefile
deleted file mode 100644
index afd84c3c6..000000000
--- a/docs/resources/PRESENTATION_ExOth/Makefile
+++ /dev/null
@@ -1,19 +0,0 @@
-PROGRAM_PREFIX :=
-
-YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
-
-all: scrambler_p01.pdf scrambler_p02.pdf equiv.log axis_test.log
-
-scrambler_p01.pdf: scrambler.ys scrambler.v
-	$(YOSYS) scrambler.ys
-
-scrambler_p02.pdf: scrambler_p01.pdf
-
-equiv.log: equiv.ys
-	$(YOSYS) -l equiv.log_new equiv.ys
-	mv equiv.log_new equiv.log
-
-axis_test.log: axis_test.ys axis_master.v axis_test.v
-	$(YOSYS) -l axis_test.log_new axis_test.ys
-	mv axis_test.log_new axis_test.log
-
diff --git a/docs/resources/PRESENTATION_ExOth/equiv.ys b/docs/resources/PRESENTATION_ExOth/equiv.ys
deleted file mode 100644
index 8db0a88a5..000000000
--- a/docs/resources/PRESENTATION_ExOth/equiv.ys
+++ /dev/null
@@ -1,17 +0,0 @@
-# read test design
-read_verilog ../PRESENTATION_ExSyn/techmap_01.v
-hierarchy -top test
-
-# create two version of the design: test_orig and test_mapped
-copy test test_orig
-rename test test_mapped
-
-# apply the techmap only to test_mapped
-techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
-
-# create a miter circuit to test equivalence
-miter -equiv -make_assert -make_outputs test_orig test_mapped miter
-flatten miter
-
-# run equivalence check
-sat -verify -prove-asserts -show-inputs -show-outputs miter
diff --git a/docs/resources/PRESENTATION_ExSyn/.gitignore b/docs/resources/PRESENTATION_ExSyn/.gitignore
deleted file mode 100644
index b4a858a01..000000000
--- a/docs/resources/PRESENTATION_ExSyn/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-*.dot
-*.pdf
diff --git a/docs/resources/PRESENTATION_Intro/.gitignore b/docs/resources/PRESENTATION_Intro/.gitignore
deleted file mode 100644
index c3cbb8c51..000000000
--- a/docs/resources/PRESENTATION_Intro/.gitignore
+++ /dev/null
@@ -1,8 +0,0 @@
-counter_00.dot
-counter_01.dot
-counter_02.dot
-counter_03.dot
-counter_00.pdf
-counter_01.pdf
-counter_02.pdf
-counter_03.pdf
diff --git a/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot b/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot
deleted file mode 100644
index 49c630080..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/cmos_00.dot
+++ /dev/null
@@ -1,34 +0,0 @@
-digraph "cmos_demo" {
-rankdir="LR";
-remincross=true;
-n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
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-n6:e -> x1:s0:w [color="black", label=""];
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot b/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot
deleted file mode 100644
index ea6f4403c..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/cmos_01.dot
+++ /dev/null
@@ -1,23 +0,0 @@
-digraph "cmos_demo" {
-rankdir="LR";
-remincross=true;
-n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
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-c14:p10:e -> n7:w [color="black", label=""];
-n7:e -> c15:p9:w [color="black", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_00.dot b/docs/source/APPNOTE_011_Design_Investigation/example_00.dot
deleted file mode 100644
index 1e23ed0ea..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/example_00.dot
+++ /dev/null
@@ -1,23 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-n4 [ shape=octagon, label="a", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="b", color="black", fontcolor="black" ];
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-p1 [shape=box, style=rounded, label="PROC $1\nexample.v:3"];
-c12:p11:e -> c14:p10:w [color="black", style="setlinewidth(3)", label=""];
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-n6:e -> p1:w [color="black", label=""];
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-p1:e -> n8:w [color="black", style="setlinewidth(3)", label=""];
-n8:e -> p1:w [color="black", style="setlinewidth(3)", label=""];
-v0:e -> c14:p9:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_01.dot b/docs/source/APPNOTE_011_Design_Investigation/example_01.dot
deleted file mode 100644
index e89292b51..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/example_01.dot
+++ /dev/null
@@ -1,33 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-n6 [ shape=octagon, label="a", color="black", fontcolor="black" ];
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-n1 [ shape=diamond, label="$0\\y[1:0]" ];
-x2:e:e -> n1:w [color="black", style="setlinewidth(3)", label=""];
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-n3 [ shape=point ];
-c20:p13:e -> n3:w [color="black", style="setlinewidth(3)", label=""];
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-n8:e -> c21:p19:w [color="black", label=""];
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-n9:e -> c18:p15:w [color="black", label=""];
-v0:e -> c21:p11:w [color="black", style="setlinewidth(3)", label=""];
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_02.dot b/docs/source/APPNOTE_011_Design_Investigation/example_02.dot
deleted file mode 100644
index f950ed2ed..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/example_02.dot
+++ /dev/null
@@ -1,20 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-n3 [ shape=octagon, label="a", color="black", fontcolor="black" ];
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diff --git a/docs/source/APPNOTE_011_Design_Investigation/example_03.dot b/docs/source/APPNOTE_011_Design_Investigation/example_03.dot
deleted file mode 100644
index e19d24af7..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/example_03.dot
+++ /dev/null
@@ -1,11 +0,0 @@
-digraph "example" {
-rankdir="LR";
-remincross=true;
-v0 [ label="a" ];
-v1 [ label="b" ];
-v2 [ label="$2_Y" ];
-c4 [ shape=record, label="{{<p1> A|<p2> B}|$2\n$add|{<p3> Y}}" ];
-v0:e -> c4:p1:w [color="black", label=""];
-v1:e -> c4:p2:w [color="black", label=""];
-c4:p3:e -> v2:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/make.sh b/docs/source/APPNOTE_011_Design_Investigation/make.sh
deleted file mode 100644
index 3845dac6b..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/make.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/bin/bash
-set -ex
-if false; then
-	rm -f *.dot
-	../../yosys example.ys
-	../../yosys -p 'proc; opt; show -format dot -prefix splice' splice.v
-	../../yosys -p 'techmap; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -format dot -prefix cmos_00' cmos.v
-	../../yosys -p 'techmap; splitnets -ports; abc -liberty ../../techlibs/cmos/cmos_cells.lib;; show -lib ../../techlibs/cmos/cmos_cells.v -format dot -prefix cmos_01' cmos.v
-	../../yosys -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
-	../../yosys -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
-	../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
-	../../yosys -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
-	../../yosys submod.ys
-	sed -i '/^label=/ d;' *.dot
-fi
-for dot_file in *.dot; do
-	pdf_file=${dot_file%.dot}.pdf
-	dot -Tpdf -o $pdf_file $dot_file
-done
diff --git a/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot b/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot
deleted file mode 100644
index 0336a9aac..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/memdemo_00.dot
+++ /dev/null
@@ -1,138 +0,0 @@
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-remincross=true;
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-n23:e -> c38:p25:w [color="black", style="setlinewidth(3)", label=""];
-c29:p26:e -> c42:p24:w [color="black", style="setlinewidth(3)", label=""];
-c30:p26:e -> c43:p24:w [color="black", style="setlinewidth(3)", label=""];
-c31:p26:e -> c40:p39:w [color="black", label=""];
-c32:p26:e -> c41:p39:w [color="black", label=""];
-c33:p26:e -> c42:p39:w [color="black", label=""];
-c34:p26:e -> c43:p39:w [color="black", label=""];
-c35:p26:e -> c31:p24:w [color="black", label=""];
-v0:e -> c31:p25:w [color="black", label=""];
-v1:e -> c32:p25:w [color="black", label=""];
-v2:e -> c33:p25:w [color="black", label=""];
-v3:e -> c34:p25:w [color="black", label=""];
-v4:e -> c35:p24:w [color="black", style="setlinewidth(3)", label=""];
-v5:e -> c36:p24:w [color="black", style="setlinewidth(3)", label=""];
-v6:e -> c37:p24:w [color="black", style="setlinewidth(3)", label=""];
-v7:e -> c38:p24:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod_02.dot b/docs/source/APPNOTE_011_Design_Investigation/submod_02.dot
deleted file mode 100644
index 1a672c484..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/submod_02.dot
+++ /dev/null
@@ -1,33 +0,0 @@
-digraph "outstage" {
-rankdir="LR";
-remincross=true;
-n4 [ shape=octagon, label="clk", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="mem[0]", color="black", fontcolor="black" ];
-n6 [ shape=octagon, label="mem[1]", color="black", fontcolor="black" ];
-n7 [ shape=octagon, label="mem[2]", color="black", fontcolor="black" ];
-n8 [ shape=octagon, label="mem[3]", color="black", fontcolor="black" ];
-n9 [ shape=octagon, label="n1", color="black", fontcolor="black" ];
-n10 [ shape=octagon, label="y", color="black", fontcolor="black" ];
-c15 [ shape=record, label="{{<p11> A|<p12> B|<p13> S}|$110\n$mux|{<p14> Y}}" ];
-x0 [ shape=record, style=rounded, label="<s0> 1:1 - 0:0 " ];
-x0:e -> c15:p13:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
-c16 [ shape=record, label="{{<p11> A|<p12> B|<p13> S}|$113\n$mux|{<p14> Y}}" ];
-x1 [ shape=record, style=rounded, label="<s0> 0:0 - 0:0 " ];
-x1:e -> c16:p13:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
-c17 [ shape=record, label="{{<p11> A|<p12> B|<p13> S}|$116\n$mux|{<p14> Y}}" ];
-x2 [ shape=record, style=rounded, label="<s0> 0:0 - 0:0 " ];
-x2:e -> c17:p13:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", label=""];
-c21 [ shape=record, label="{{<p18> CLK|<p19> D}|$64\n$dff|{<p20> Q}}" ];
-c15:p14:e -> c21:p19:w [color="black", style="setlinewidth(3)", label=""];
-c21:p20:e -> n10:w [color="black", style="setlinewidth(3)", label=""];
-c16:p14:e -> c15:p11:w [color="black", style="setlinewidth(3)", label=""];
-c17:p14:e -> c15:p12:w [color="black", style="setlinewidth(3)", label=""];
-n4:e -> c21:p18:w [color="black", label=""];
-n5:e -> c16:p11:w [color="black", style="setlinewidth(3)", label=""];
-n6:e -> c16:p12:w [color="black", style="setlinewidth(3)", label=""];
-n7:e -> c17:p11:w [color="black", style="setlinewidth(3)", label=""];
-n8:e -> c17:p12:w [color="black", style="setlinewidth(3)", label=""];
-n9:e -> x0:s0:w [color="black", label=""];
-n9:e -> x1:s0:w [color="black", label=""];
-n9:e -> x2:s0:w [color="black", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod_03.dot b/docs/source/APPNOTE_011_Design_Investigation/submod_03.dot
deleted file mode 100644
index 0dbbe3baa..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/submod_03.dot
+++ /dev/null
@@ -1,26 +0,0 @@
-digraph "selstage" {
-rankdir="LR";
-remincross=true;
-n3 [ shape=octagon, label="d", color="black", fontcolor="black" ];
-n4 [ shape=octagon, label="n1", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="n2", color="black", fontcolor="black" ];
-n6 [ shape=octagon, label="s1", color="black", fontcolor="black" ];
-n7 [ shape=octagon, label="s2", color="black", fontcolor="black" ];
-c10 [ shape=record, label="{{<p8> A}|$39\n$reduce_bool|{<p9> Y}}" ];
-v0 [ label="4'0000" ];
-c13 [ shape=record, label="{{<p8> A|<p11> B|<p12> S}|$40\n$mux|{<p9> Y}}" ];
-x1 [ shape=record, style=rounded, label="<s1> 3:2 - 1:0 |<s0> 1:0 - 1:0 " ];
-c13:p9:e -> x1:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", style="setlinewidth(3)", label=""];
-c14 [ shape=record, label="{{<p8> A|<p11> B}|$38\n$xor|{<p9> Y}}" ];
-x2 [ shape=record, style=rounded, label="<s1> 1:0 - 3:2 |<s0> 1:0 - 1:0 " ];
-x2:e -> c14:p8:w [arrowhead=odiamond, arrowtail=odiamond, dir=both, color="black", style="setlinewidth(3)", label=""];
-c10:p9:e -> c13:p12:w [color="black", label=""];
-c14:p9:e -> c13:p11:w [color="black", style="setlinewidth(3)", label=""];
-n3:e -> c10:p8:w [color="black", style="setlinewidth(3)", label=""];
-n3:e -> c14:p11:w [color="black", style="setlinewidth(3)", label=""];
-x1:s0:e -> n4:w [color="black", style="setlinewidth(3)", label=""];
-x1:s1:e -> n5:w [color="black", style="setlinewidth(3)", label=""];
-n6:e -> x2:s1:w [color="black", style="setlinewidth(3)", label=""];
-n7:e -> x2:s0:w [color="black", style="setlinewidth(3)", label=""];
-v0:e -> c13:p8:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_00.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_00.dot
deleted file mode 100644
index 06522dcc9..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/sumprod_00.dot
+++ /dev/null
@@ -1,18 +0,0 @@
-digraph "sumprod" {
-rankdir="LR";
-remincross=true;
-v0 [ label="a" ];
-v1 [ label="b" ];
-v2 [ label="$1_Y" ];
-c4 [ shape=record, label="{{<p1> A|<p2> B}|$1\n$add|{<p3> Y}}" ];
-v3 [ label="$1_Y" ];
-v4 [ label="c" ];
-v5 [ label="sum" ];
-c5 [ shape=record, label="{{<p1> A|<p2> B}|$2\n$add|{<p3> Y}}" ];
-v0:e -> c4:p1:w [color="black", style="setlinewidth(3)", label=""];
-v1:e -> c4:p2:w [color="black", style="setlinewidth(3)", label=""];
-c4:p3:e -> v2:w [color="black", style="setlinewidth(3)", label=""];
-v3:e -> c5:p1:w [color="black", style="setlinewidth(3)", label=""];
-v4:e -> c5:p2:w [color="black", style="setlinewidth(3)", label=""];
-c5:p3:e -> v5:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_01.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_01.dot
deleted file mode 100644
index aefe7a6da..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/sumprod_01.dot
+++ /dev/null
@@ -1,15 +0,0 @@
-digraph "sumprod" {
-rankdir="LR";
-remincross=true;
-n2 [ shape=octagon, label="a", color="black", fontcolor="black" ];
-n3 [ shape=octagon, label="b", color="black", fontcolor="black" ];
-n4 [ shape=octagon, label="c", color="black", fontcolor="black" ];
-n5 [ shape=octagon, label="sum", color="black", fontcolor="black" ];
-c9 [ shape=record, label="{{<p6> A|<p7> B}|$1\n$add|{<p8> Y}}" ];
-c10 [ shape=record, label="{{<p6> A|<p7> B}|$2\n$add|{<p8> Y}}" ];
-c9:p8:e -> c10:p6:w [color="black", style="setlinewidth(3)", label=""];
-n2:e -> c9:p6:w [color="black", style="setlinewidth(3)", label=""];
-n3:e -> c9:p7:w [color="black", style="setlinewidth(3)", label=""];
-n4:e -> c10:p7:w [color="black", style="setlinewidth(3)", label=""];
-c10:p8:e -> n5:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_02.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_02.dot
deleted file mode 100644
index 4646c9947..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/sumprod_02.dot
+++ /dev/null
@@ -1,5 +0,0 @@
-digraph "sumprod" {
-rankdir="LR";
-remincross=true;
-n1 [ shape=octagon, label="prod", color="black", fontcolor="black" ];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_03.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_03.dot
deleted file mode 100644
index dcfea2b56..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/sumprod_03.dot
+++ /dev/null
@@ -1,11 +0,0 @@
-digraph "sumprod" {
-rankdir="LR";
-remincross=true;
-n1 [ shape=octagon, label="prod", color="black", fontcolor="black" ];
-v0 [ label="$3_Y" ];
-v1 [ label="c" ];
-c5 [ shape=record, label="{{<p2> A|<p3> B}|$4\n$mul|{<p4> Y}}" ];
-c5:p4:e -> n1:w [color="black", style="setlinewidth(3)", label=""];
-v0:e -> c5:p2:w [color="black", style="setlinewidth(3)", label=""];
-v1:e -> c5:p3:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_04.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_04.dot
deleted file mode 100644
index e77c41aa2..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/sumprod_04.dot
+++ /dev/null
@@ -1,11 +0,0 @@
-digraph "sumprod" {
-rankdir="LR";
-remincross=true;
-n2 [ shape=octagon, label="c", color="black", fontcolor="black" ];
-n3 [ shape=octagon, label="prod", color="black", fontcolor="black" ];
-c7 [ shape=record, label="{{<p4> A|<p5> B}|$4\n$mul|{<p6> Y}}" ];
-n1 [ shape=diamond, label="$3_Y" ];
-n1:e -> c7:p4:w [color="black", style="setlinewidth(3)", label=""];
-n2:e -> c7:p5:w [color="black", style="setlinewidth(3)", label=""];
-c7:p6:e -> n3:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod_05.dot b/docs/source/APPNOTE_011_Design_Investigation/sumprod_05.dot
deleted file mode 100644
index b54441290..000000000
--- a/docs/source/APPNOTE_011_Design_Investigation/sumprod_05.dot
+++ /dev/null
@@ -1,15 +0,0 @@
-digraph "sumprod" {
-rankdir="LR";
-remincross=true;
-n2 [ shape=octagon, label="c", color="black", fontcolor="black" ];
-n3 [ shape=octagon, label="prod", color="black", fontcolor="black" ];
-v0 [ label="a" ];
-v1 [ label="b" ];
-c7 [ shape=record, label="{{<p4> A|<p5> B}|$3\n$mul|{<p6> Y}}" ];
-c8 [ shape=record, label="{{<p4> A|<p5> B}|$4\n$mul|{<p6> Y}}" ];
-c7:p6:e -> c8:p4:w [color="black", style="setlinewidth(3)", label=""];
-n2:e -> c8:p5:w [color="black", style="setlinewidth(3)", label=""];
-c8:p6:e -> n3:w [color="black", style="setlinewidth(3)", label=""];
-v0:e -> c7:p4:w [color="black", style="setlinewidth(3)", label=""];
-v1:e -> c7:p5:w [color="black", style="setlinewidth(3)", label=""];
-}
diff --git a/docs/resources/PRESENTATION_ExAdv/.gitignore b/docs/source/code_examples/.gitignore
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/.gitignore
rename to docs/source/code_examples/.gitignore
diff --git a/docs/resources/PRESENTATION_ExOth/axis_master.v b/docs/source/code_examples/axis/axis_master.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExOth/axis_master.v
rename to docs/source/code_examples/axis/axis_master.v
diff --git a/docs/resources/PRESENTATION_ExOth/axis_test.v b/docs/source/code_examples/axis/axis_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExOth/axis_test.v
rename to docs/source/code_examples/axis/axis_test.v
diff --git a/docs/resources/PRESENTATION_ExOth/axis_test.ys b/docs/source/code_examples/axis/axis_test.ys
similarity index 70%
rename from docs/resources/PRESENTATION_ExOth/axis_test.ys
rename to docs/source/code_examples/axis/axis_test.ys
index 19663ac77..a55d017d9 100644
--- a/docs/resources/PRESENTATION_ExOth/axis_test.ys
+++ b/docs/source/code_examples/axis/axis_test.ys
@@ -2,4 +2,4 @@ read_verilog -sv axis_master.v axis_test.v
 hierarchy -top axis_test
 
 proc; flatten;;
-sat -falsify -seq 50 -prove-asserts
+sat -seq 50 -prove-asserts
diff --git a/docs/resources/PRESENTATION_Intro/Makefile b/docs/source/code_examples/intro/Makefile
similarity index 100%
rename from docs/resources/PRESENTATION_Intro/Makefile
rename to docs/source/code_examples/intro/Makefile
diff --git a/docs/resources/PRESENTATION_Intro/counter.v b/docs/source/code_examples/intro/counter.v
similarity index 100%
rename from docs/resources/PRESENTATION_Intro/counter.v
rename to docs/source/code_examples/intro/counter.v
diff --git a/docs/resources/PRESENTATION_Intro/counter.ys b/docs/source/code_examples/intro/counter.ys
similarity index 100%
rename from docs/resources/PRESENTATION_Intro/counter.ys
rename to docs/source/code_examples/intro/counter.ys
diff --git a/docs/resources/PRESENTATION_Intro/counter_outputs.ys b/docs/source/code_examples/intro/counter_outputs.ys
similarity index 100%
rename from docs/resources/PRESENTATION_Intro/counter_outputs.ys
rename to docs/source/code_examples/intro/counter_outputs.ys
diff --git a/docs/resources/PRESENTATION_Intro/mycells.lib b/docs/source/code_examples/intro/mycells.lib
similarity index 100%
rename from docs/resources/PRESENTATION_Intro/mycells.lib
rename to docs/source/code_examples/intro/mycells.lib
diff --git a/docs/resources/PRESENTATION_Intro/mycells.v b/docs/source/code_examples/intro/mycells.v
similarity index 100%
rename from docs/resources/PRESENTATION_Intro/mycells.v
rename to docs/source/code_examples/intro/mycells.v
diff --git a/docs/source/code_examples/macc/Makefile b/docs/source/code_examples/macc/Makefile
new file mode 100644
index 000000000..91ec83288
--- /dev/null
+++ b/docs/source/code_examples/macc/Makefile
@@ -0,0 +1,12 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: macc_simple_xmap.pdf macc_xilinx_xmap.pdf
+
+macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+	$(YOSYS) macc_simple_test.ys
+
+macc_xilinx_xmap.pdf: macc_xilinx_*.v macc_xilinx_test.ys
+	$(YOSYS) macc_xilinx_test.ys
+
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_simple_test.v b/docs/source/code_examples/macc/macc_simple_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_simple_test.v
rename to docs/source/code_examples/macc/macc_simple_test.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_simple_test.ys b/docs/source/code_examples/macc/macc_simple_test.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_simple_test.ys
rename to docs/source/code_examples/macc/macc_simple_test.ys
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_simple_test_01.v b/docs/source/code_examples/macc/macc_simple_test_01.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_simple_test_01.v
rename to docs/source/code_examples/macc/macc_simple_test_01.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_simple_test_02.v b/docs/source/code_examples/macc/macc_simple_test_02.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_simple_test_02.v
rename to docs/source/code_examples/macc/macc_simple_test_02.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_simple_xmap.v b/docs/source/code_examples/macc/macc_simple_xmap.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_simple_xmap.v
rename to docs/source/code_examples/macc/macc_simple_xmap.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v b/docs/source/code_examples/macc/macc_xilinx_swap_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
rename to docs/source/code_examples/macc/macc_xilinx_swap_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v b/docs/source/code_examples/macc/macc_xilinx_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v
rename to docs/source/code_examples/macc/macc_xilinx_test.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.ys b/docs/source/code_examples/macc/macc_xilinx_test.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.ys
rename to docs/source/code_examples/macc/macc_xilinx_test.ys
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v b/docs/source/code_examples/macc/macc_xilinx_unwrap_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
rename to docs/source/code_examples/macc/macc_xilinx_unwrap_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v b/docs/source/code_examples/macc/macc_xilinx_wrap_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
rename to docs/source/code_examples/macc/macc_xilinx_wrap_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v b/docs/source/code_examples/macc/macc_xilinx_xmap.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v
rename to docs/source/code_examples/macc/macc_xilinx_xmap.v
diff --git a/docs/source/APPNOTE_011_Design_Investigation/primetest.v b/docs/source/code_examples/primetest.v
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/primetest.v
rename to docs/source/code_examples/primetest.v
diff --git a/docs/source/code_examples/scrambler/Makefile b/docs/source/code_examples/scrambler/Makefile
new file mode 100644
index 000000000..1e9425558
--- /dev/null
+++ b/docs/source/code_examples/scrambler/Makefile
@@ -0,0 +1,8 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: scrambler_p01.dot scrambler_p02.dot
+
+scrambler_p01.dot scrambler_p02.dot: scrambler.ys scrambler.v
+	$(YOSYS) scrambler.ys
diff --git a/docs/resources/PRESENTATION_ExOth/scrambler.v b/docs/source/code_examples/scrambler/scrambler.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExOth/scrambler.v
rename to docs/source/code_examples/scrambler/scrambler.v
diff --git a/docs/resources/PRESENTATION_ExOth/scrambler.ys b/docs/source/code_examples/scrambler/scrambler.ys
similarity index 69%
rename from docs/resources/PRESENTATION_ExOth/scrambler.ys
rename to docs/source/code_examples/scrambler/scrambler.ys
index 2ef14c56e..f14caa6f7 100644
--- a/docs/resources/PRESENTATION_ExOth/scrambler.ys
+++ b/docs/source/code_examples/scrambler/scrambler.ys
@@ -1,4 +1,3 @@
-
 read_verilog scrambler.v
 
 hierarchy; proc;;
@@ -7,8 +6,8 @@ cd scrambler
 submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
 cd ..
 
-show -prefix scrambler_p01 -format pdf -notitle scrambler
-show -prefix scrambler_p02 -format pdf -notitle xorshift32
+show -prefix scrambler_p01 -format dot -notitle scrambler
+show -prefix scrambler_p02 -format dot -notitle xorshift32
 
 echo on
 
diff --git a/docs/source/code_examples/selections/Makefile b/docs/source/code_examples/selections/Makefile
new file mode 100644
index 000000000..384ce12a9
--- /dev/null
+++ b/docs/source/code_examples/selections/Makefile
@@ -0,0 +1,32 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+SUMPROD = sumprod_00 sumprod_01 sumprod_02 sumprod_03 sumprod_04 sumprod_05
+SUMPROD_DOTS := $(addsuffix .dot,$(SUMPROD))
+
+MEMDEMO = memdemo_00 memdemo_01
+MEMDEMO_DOTS := $(addsuffix .dot,$(MEMDEMO))
+
+SUBMOD = submod_00 submod_01 submod_02 submod_03
+SUBMOD_DOTS := $(addsuffix .dot,$(SUBMOD))
+
+all: select.dot $(SUMPROD_DOTS) $(MEMDEMO_DOTS)
+
+select.dot: select.v select.ys
+	$(YOSYS) select.ys
+
+$(SUMPROD_DOTS): sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff; show -format dot -prefix sumprod_00' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select a:sumstuff %x; show -format dot -prefix sumprod_01' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod; show -format dot -prefix sumprod_02' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod %ci; show -format dot -prefix sumprod_03' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod %ci2; show -format dot -prefix sumprod_04' sumprod.v
+	$(YOSYS) -p 'opt; cd sumprod; select prod %ci3; show -format dot -prefix sumprod_05' sumprod.v
+
+$(MEMDEMO_DOTS): memdemo.v
+	$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_00' memdemo.v
+	$(YOSYS) -p 'proc; opt; memory; opt; cd memdemo; show -format dot -prefix memdemo_01 y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff' memdemo.v
+
+$(SUBMOD_DOTS): submod.ys memdemo.v
+	$(YOSYS) submod.ys
diff --git a/docs/source/APPNOTE_011_Design_Investigation/foobaraddsub.v b/docs/source/code_examples/selections/foobaraddsub.v
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/foobaraddsub.v
rename to docs/source/code_examples/selections/foobaraddsub.v
diff --git a/docs/source/APPNOTE_011_Design_Investigation/memdemo.v b/docs/source/code_examples/selections/memdemo.v
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/memdemo.v
rename to docs/source/code_examples/selections/memdemo.v
diff --git a/docs/resources/PRESENTATION_ExAdv/select.v b/docs/source/code_examples/selections/select.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/select.v
rename to docs/source/code_examples/selections/select.v
diff --git a/docs/resources/PRESENTATION_ExAdv/select.ys b/docs/source/code_examples/selections/select.ys
similarity index 85%
rename from docs/resources/PRESENTATION_ExAdv/select.ys
rename to docs/source/code_examples/selections/select.ys
index 9832c104b..565ce90a3 100644
--- a/docs/resources/PRESENTATION_ExAdv/select.ys
+++ b/docs/source/code_examples/selections/select.ys
@@ -5,6 +5,6 @@ cd test
 select -set cone_a state_a %ci*:-$dff
 select -set cone_b state_b %ci*:-$dff
 select -set cone_ab @cone_a @cone_b %i
-show -prefix select -format pdf -notitle \
+show -prefix select -format dot -notitle \
      -color red @cone_ab -color magenta @cone_a \
      -color blue @cone_b
diff --git a/docs/source/APPNOTE_011_Design_Investigation/submod.ys b/docs/source/code_examples/selections/submod.ys
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/submod.ys
rename to docs/source/code_examples/selections/submod.ys
diff --git a/docs/source/APPNOTE_011_Design_Investigation/sumprod.v b/docs/source/code_examples/selections/sumprod.v
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/sumprod.v
rename to docs/source/code_examples/selections/sumprod.v
diff --git a/docs/source/code_examples/show/Makefile b/docs/source/code_examples/show/Makefile
new file mode 100644
index 000000000..9cc4fc58d
--- /dev/null
+++ b/docs/source/code_examples/show/Makefile
@@ -0,0 +1,23 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
+
+EXAMPLE = example_00 example_01 example_02 example_03
+EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
+
+CMOS = cmos_00 cmos_01
+CMOS_DOTS := $(addsuffix .dot,$(CMOS))
+
+all: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
+
+splice.dot: splice.v
+	$(YOSYS) -p 'proc; opt; show -format dot -prefix splice' splice.v
+
+$(EXAMPLE_DOTS): example.v example.ys
+	$(YOSYS) example.ys
+
+cmos_00.dot: cmos.v
+	$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
+
+cmos_01.dot: cmos.v
+	$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'
diff --git a/docs/source/APPNOTE_011_Design_Investigation/cmos.v b/docs/source/code_examples/show/cmos.v
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/cmos.v
rename to docs/source/code_examples/show/cmos.v
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example.v b/docs/source/code_examples/show/example.v
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/example.v
rename to docs/source/code_examples/show/example.v
diff --git a/docs/source/APPNOTE_011_Design_Investigation/example.ys b/docs/source/code_examples/show/example.ys
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/example.ys
rename to docs/source/code_examples/show/example.ys
diff --git a/docs/source/APPNOTE_011_Design_Investigation/splice.v b/docs/source/code_examples/show/splice.v
similarity index 100%
rename from docs/source/APPNOTE_011_Design_Investigation/splice.v
rename to docs/source/code_examples/show/splice.v
diff --git a/docs/source/CHAPTER_Prog/.gitignore b/docs/source/code_examples/stubnets/.gitignore
similarity index 100%
rename from docs/source/CHAPTER_Prog/.gitignore
rename to docs/source/code_examples/stubnets/.gitignore
diff --git a/docs/source/CHAPTER_Prog/Makefile b/docs/source/code_examples/stubnets/Makefile
similarity index 100%
rename from docs/source/CHAPTER_Prog/Makefile
rename to docs/source/code_examples/stubnets/Makefile
diff --git a/docs/source/CHAPTER_Prog/stubnets.cc b/docs/source/code_examples/stubnets/stubnets.cc
similarity index 100%
rename from docs/source/CHAPTER_Prog/stubnets.cc
rename to docs/source/code_examples/stubnets/stubnets.cc
diff --git a/docs/source/CHAPTER_Prog/test.v b/docs/source/code_examples/stubnets/test.v
similarity index 100%
rename from docs/source/CHAPTER_Prog/test.v
rename to docs/source/code_examples/stubnets/test.v
diff --git a/docs/resources/PRESENTATION_ExSyn/Makefile b/docs/source/code_examples/synth_flow/Makefile
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/Makefile
rename to docs/source/code_examples/synth_flow/Makefile
diff --git a/docs/resources/PRESENTATION_ExSyn/abc_01.v b/docs/source/code_examples/synth_flow/abc_01.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/abc_01.v
rename to docs/source/code_examples/synth_flow/abc_01.v
diff --git a/docs/resources/PRESENTATION_ExSyn/abc_01.ys b/docs/source/code_examples/synth_flow/abc_01.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/abc_01.ys
rename to docs/source/code_examples/synth_flow/abc_01.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/abc_01_cells.lib b/docs/source/code_examples/synth_flow/abc_01_cells.lib
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/abc_01_cells.lib
rename to docs/source/code_examples/synth_flow/abc_01_cells.lib
diff --git a/docs/resources/PRESENTATION_ExSyn/abc_01_cells.v b/docs/source/code_examples/synth_flow/abc_01_cells.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/abc_01_cells.v
rename to docs/source/code_examples/synth_flow/abc_01_cells.v
diff --git a/docs/resources/PRESENTATION_ExSyn/memory_01.v b/docs/source/code_examples/synth_flow/memory_01.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/memory_01.v
rename to docs/source/code_examples/synth_flow/memory_01.v
diff --git a/docs/resources/PRESENTATION_ExSyn/memory_01.ys b/docs/source/code_examples/synth_flow/memory_01.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/memory_01.ys
rename to docs/source/code_examples/synth_flow/memory_01.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/memory_02.v b/docs/source/code_examples/synth_flow/memory_02.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/memory_02.v
rename to docs/source/code_examples/synth_flow/memory_02.v
diff --git a/docs/resources/PRESENTATION_ExSyn/memory_02.ys b/docs/source/code_examples/synth_flow/memory_02.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/memory_02.ys
rename to docs/source/code_examples/synth_flow/memory_02.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_01.v b/docs/source/code_examples/synth_flow/opt_01.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_01.v
rename to docs/source/code_examples/synth_flow/opt_01.v
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_01.ys b/docs/source/code_examples/synth_flow/opt_01.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_01.ys
rename to docs/source/code_examples/synth_flow/opt_01.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_02.v b/docs/source/code_examples/synth_flow/opt_02.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_02.v
rename to docs/source/code_examples/synth_flow/opt_02.v
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_02.ys b/docs/source/code_examples/synth_flow/opt_02.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_02.ys
rename to docs/source/code_examples/synth_flow/opt_02.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_03.v b/docs/source/code_examples/synth_flow/opt_03.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_03.v
rename to docs/source/code_examples/synth_flow/opt_03.v
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_03.ys b/docs/source/code_examples/synth_flow/opt_03.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_03.ys
rename to docs/source/code_examples/synth_flow/opt_03.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_04.v b/docs/source/code_examples/synth_flow/opt_04.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_04.v
rename to docs/source/code_examples/synth_flow/opt_04.v
diff --git a/docs/resources/PRESENTATION_ExSyn/opt_04.ys b/docs/source/code_examples/synth_flow/opt_04.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/opt_04.ys
rename to docs/source/code_examples/synth_flow/opt_04.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/proc_01.v b/docs/source/code_examples/synth_flow/proc_01.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/proc_01.v
rename to docs/source/code_examples/synth_flow/proc_01.v
diff --git a/docs/resources/PRESENTATION_ExSyn/proc_01.ys b/docs/source/code_examples/synth_flow/proc_01.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/proc_01.ys
rename to docs/source/code_examples/synth_flow/proc_01.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/proc_02.v b/docs/source/code_examples/synth_flow/proc_02.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/proc_02.v
rename to docs/source/code_examples/synth_flow/proc_02.v
diff --git a/docs/resources/PRESENTATION_ExSyn/proc_02.ys b/docs/source/code_examples/synth_flow/proc_02.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/proc_02.ys
rename to docs/source/code_examples/synth_flow/proc_02.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/proc_03.v b/docs/source/code_examples/synth_flow/proc_03.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/proc_03.v
rename to docs/source/code_examples/synth_flow/proc_03.v
diff --git a/docs/resources/PRESENTATION_ExSyn/proc_03.ys b/docs/source/code_examples/synth_flow/proc_03.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/proc_03.ys
rename to docs/source/code_examples/synth_flow/proc_03.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/techmap_01.v b/docs/source/code_examples/synth_flow/techmap_01.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/techmap_01.v
rename to docs/source/code_examples/synth_flow/techmap_01.v
diff --git a/docs/resources/PRESENTATION_ExSyn/techmap_01.ys b/docs/source/code_examples/synth_flow/techmap_01.ys
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/techmap_01.ys
rename to docs/source/code_examples/synth_flow/techmap_01.ys
diff --git a/docs/resources/PRESENTATION_ExSyn/techmap_01_map.v b/docs/source/code_examples/synth_flow/techmap_01_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExSyn/techmap_01_map.v
rename to docs/source/code_examples/synth_flow/techmap_01_map.v
diff --git a/docs/source/code_examples/techmap/Makefile b/docs/source/code_examples/techmap/Makefile
new file mode 100644
index 000000000..b48972fd9
--- /dev/null
+++ b/docs/source/code_examples/techmap/Makefile
@@ -0,0 +1,21 @@
+PROGRAM_PREFIX :=
+
+YOSYS ?= ../../../$(PROGRAM_PREFIX)yosys
+
+all: red_or3x1.dot sym_mul.dot mymul.dot mulshift.dot addshift.dot
+
+red_or3x1.dot: red_or3x1_*
+	$(YOSYS) red_or3x1_test.ys
+
+sym_mul.dot: sym_mul_*
+	$(YOSYS) sym_mul_test.ys
+
+mymul.dot: mymul_*
+	$(YOSYS) mymul_test.ys
+
+mulshift.dot: mulshift_*
+	$(YOSYS) mulshift_test.ys
+
+addshift.dot: addshift_*
+	$(YOSYS) addshift_test.ys
+
diff --git a/docs/resources/PRESENTATION_ExAdv/addshift_map.v b/docs/source/code_examples/techmap/addshift_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/addshift_map.v
rename to docs/source/code_examples/techmap/addshift_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/addshift_test.v b/docs/source/code_examples/techmap/addshift_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/addshift_test.v
rename to docs/source/code_examples/techmap/addshift_test.v
diff --git a/docs/resources/PRESENTATION_ExAdv/addshift_test.ys b/docs/source/code_examples/techmap/addshift_test.ys
similarity index 67%
rename from docs/resources/PRESENTATION_ExAdv/addshift_test.ys
rename to docs/source/code_examples/techmap/addshift_test.ys
index c08f1106a..c15691b33 100644
--- a/docs/resources/PRESENTATION_ExAdv/addshift_test.ys
+++ b/docs/source/code_examples/techmap/addshift_test.ys
@@ -3,4 +3,4 @@ hierarchy -check -top test
 
 techmap -map addshift_map.v;;
 
-show -prefix addshift -format pdf -notitle
+show -prefix addshift -format dot -notitle
diff --git a/docs/resources/PRESENTATION_ExAdv/mulshift_map.v b/docs/source/code_examples/techmap/mulshift_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/mulshift_map.v
rename to docs/source/code_examples/techmap/mulshift_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/mulshift_test.v b/docs/source/code_examples/techmap/mulshift_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/mulshift_test.v
rename to docs/source/code_examples/techmap/mulshift_test.v
diff --git a/docs/resources/PRESENTATION_ExAdv/mulshift_test.ys b/docs/source/code_examples/techmap/mulshift_test.ys
similarity index 64%
rename from docs/resources/PRESENTATION_ExAdv/mulshift_test.ys
rename to docs/source/code_examples/techmap/mulshift_test.ys
index c5dac49eb..79daaf0c4 100644
--- a/docs/resources/PRESENTATION_ExAdv/mulshift_test.ys
+++ b/docs/source/code_examples/techmap/mulshift_test.ys
@@ -4,4 +4,4 @@ hierarchy -check -top test
 techmap -map sym_mul_map.v \
         -map mulshift_map.v;;
 
-show -prefix mulshift -format pdf -notitle -lib sym_mul_cells.v
+show -prefix mulshift -format dot -notitle -lib sym_mul_cells.v
diff --git a/docs/resources/PRESENTATION_ExAdv/mymul_map.v b/docs/source/code_examples/techmap/mymul_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/mymul_map.v
rename to docs/source/code_examples/techmap/mymul_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/mymul_test.v b/docs/source/code_examples/techmap/mymul_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/mymul_test.v
rename to docs/source/code_examples/techmap/mymul_test.v
diff --git a/docs/resources/PRESENTATION_ExAdv/mymul_test.ys b/docs/source/code_examples/techmap/mymul_test.ys
similarity index 84%
rename from docs/resources/PRESENTATION_ExAdv/mymul_test.ys
rename to docs/source/code_examples/techmap/mymul_test.ys
index 48203e319..b7176fdc4 100644
--- a/docs/resources/PRESENTATION_ExAdv/mymul_test.ys
+++ b/docs/source/code_examples/techmap/mymul_test.ys
@@ -12,4 +12,4 @@ flatten miter
 sat -verify -prove trigger 0 miter
 
 splitnets -ports test_mapped/A
-show -prefix mymul -format pdf -notitle test_mapped
+show -prefix mymul -format dot -notitle test_mapped
diff --git a/docs/resources/PRESENTATION_ExAdv/red_or3x1_cells.v b/docs/source/code_examples/techmap/red_or3x1_cells.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/red_or3x1_cells.v
rename to docs/source/code_examples/techmap/red_or3x1_cells.v
diff --git a/docs/resources/PRESENTATION_ExAdv/red_or3x1_map.v b/docs/source/code_examples/techmap/red_or3x1_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/red_or3x1_map.v
rename to docs/source/code_examples/techmap/red_or3x1_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/red_or3x1_test.v b/docs/source/code_examples/techmap/red_or3x1_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/red_or3x1_test.v
rename to docs/source/code_examples/techmap/red_or3x1_test.v
diff --git a/docs/resources/PRESENTATION_ExAdv/red_or3x1_test.ys b/docs/source/code_examples/techmap/red_or3x1_test.ys
similarity index 63%
rename from docs/resources/PRESENTATION_ExAdv/red_or3x1_test.ys
rename to docs/source/code_examples/techmap/red_or3x1_test.ys
index b92346034..891b8177b 100644
--- a/docs/resources/PRESENTATION_ExAdv/red_or3x1_test.ys
+++ b/docs/source/code_examples/techmap/red_or3x1_test.ys
@@ -4,4 +4,4 @@ hierarchy -check -top test
 techmap -map red_or3x1_map.v;;
 
 splitnets -ports
-show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v
+show -prefix red_or3x1 -format dot -notitle -lib red_or3x1_cells.v
diff --git a/docs/resources/PRESENTATION_ExAdv/sym_mul_cells.v b/docs/source/code_examples/techmap/sym_mul_cells.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/sym_mul_cells.v
rename to docs/source/code_examples/techmap/sym_mul_cells.v
diff --git a/docs/resources/PRESENTATION_ExAdv/sym_mul_map.v b/docs/source/code_examples/techmap/sym_mul_map.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/sym_mul_map.v
rename to docs/source/code_examples/techmap/sym_mul_map.v
diff --git a/docs/resources/PRESENTATION_ExAdv/sym_mul_test.v b/docs/source/code_examples/techmap/sym_mul_test.v
similarity index 100%
rename from docs/resources/PRESENTATION_ExAdv/sym_mul_test.v
rename to docs/source/code_examples/techmap/sym_mul_test.v
diff --git a/docs/resources/PRESENTATION_ExAdv/sym_mul_test.ys b/docs/source/code_examples/techmap/sym_mul_test.ys
similarity index 57%
rename from docs/resources/PRESENTATION_ExAdv/sym_mul_test.ys
rename to docs/source/code_examples/techmap/sym_mul_test.ys
index 0c07e7e87..f19bee64a 100644
--- a/docs/resources/PRESENTATION_ExAdv/sym_mul_test.ys
+++ b/docs/source/code_examples/techmap/sym_mul_test.ys
@@ -3,4 +3,4 @@ hierarchy -check -top test
 
 techmap -map sym_mul_map.v;;
 
-show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v
+show -prefix sym_mul -format dot -notitle -lib sym_mul_cells.v
diff --git a/docs/source/getting_started/examples.rst b/docs/source/getting_started/examples.rst
index 8342b685c..8fecb4985 100644
--- a/docs/source/getting_started/examples.rst
+++ b/docs/source/getting_started/examples.rst
@@ -53,13 +53,13 @@ Simple synthesis script
 ~~~~~~~~~~~~~~~~~~~~~~~
 
 This section covers an example project available in
-``docs/resources/PRESENTATION_Intro/*``.  The project contains a simple ASIC
+``docs/source/code_examples/intro/*``.  The project contains a simple ASIC
 synthesis script (``counter.ys``), a digital design written in Verilog
 (``counter.v``), and a simple CMOS cell library (``mycells.lib``).
 
-.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
+.. literalinclude:: /code_examples/intro/counter.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_Intro/counter.ys``
+   :caption: ``docs/source/code_examples/intro/counter.ys``
 
 .. role:: yoscrypt(code)
    :language: yoscrypt
@@ -89,18 +89,18 @@ synthesis script (``counter.ys``), a digital design written in Verilog
 Running the script
 ^^^^^^^^^^^^^^^^^^
 
-.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.v
+.. literalinclude:: /code_examples/intro/counter.v
    :language: Verilog
-   :caption: ``docs/resources/PRESENTATION_Intro/counter.v``
+   :caption: ``docs/source/code_examples/intro/counter.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_Intro/mycells.lib
+.. literalinclude:: /code_examples/intro/mycells.lib
    :language: Liberty
-   :caption: ``docs/resources/PRESENTATION_Intro/mycells.lib``
+   :caption: ``docs/source/code_examples/intro/mycells.lib``
 
 Step 1
 """"""
 
-.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
+.. literalinclude:: /code_examples/intro/counter.ys
    :language: yoscrypt
    :lines: 1-3
 
@@ -112,7 +112,7 @@ Result:
 Step 2
 """"""
 
-.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
+.. literalinclude:: /code_examples/intro/counter.ys
    :language: yoscrypt
    :lines: 5-6
 
@@ -124,7 +124,7 @@ Result:
 Step 3
 """"""
 
-.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
+.. literalinclude:: /code_examples/intro/counter.ys
    :language: yoscrypt
    :lines: 8-9
 
@@ -136,7 +136,7 @@ Result:
 Step 4
 """"""
 
-.. literalinclude:: ../../resources/PRESENTATION_Intro/counter.ys
+.. literalinclude:: /code_examples/intro/counter.ys
    :language: yoscrypt
    :lines: 11-18
 
diff --git a/docs/source/getting_started/typical_phases.rst b/docs/source/getting_started/typical_phases.rst
index a06ee1e17..d04419ec1 100644
--- a/docs/source/getting_started/typical_phases.rst
+++ b/docs/source/getting_started/typical_phases.rst
@@ -86,13 +86,13 @@ after design elaboration.
 Example
 ^^^^^^^
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_01.v
+.. literalinclude:: /code_examples/synth_flow/proc_01.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.v``
+   :caption: ``docs/source/code_examples/synth_flow/proc_01.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_01.ys
+.. literalinclude:: /code_examples/synth_flow/proc_01.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/proc_01.ys``
+   :caption: ``docs/source/code_examples/synth_flow/proc_01.ys``
 
 .. figure:: /_images/res/PRESENTATION_ExSyn/proc_01.*
     :class: width-helper
@@ -100,24 +100,24 @@ Example
 .. figure:: /_images/res/PRESENTATION_ExSyn/proc_02.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.v
+.. literalinclude:: /code_examples/synth_flow/proc_02.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.v``
+   :caption: ``docs/source/code_examples/synth_flow/proc_02.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_02.ys
+.. literalinclude:: /code_examples/synth_flow/proc_02.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/proc_02.ys``
+   :caption: ``docs/source/code_examples/synth_flow/proc_02.ys``
 
 .. figure:: /_images/res/PRESENTATION_ExSyn/proc_03.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.ys
+.. literalinclude:: /code_examples/synth_flow/proc_03.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/proc_03.ys``
+   :caption: ``docs/source/code_examples/synth_flow/proc_03.ys``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/proc_03.v
+.. literalinclude:: /code_examples/synth_flow/proc_03.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/proc_03.v``
+   :caption: ``docs/source/code_examples/synth_flow/proc_03.v``
 
 
 The :cmd:ref:`opt` command
@@ -153,46 +153,46 @@ Example
 .. figure:: /_images/res/PRESENTATION_ExSyn/opt_01.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.ys
+.. literalinclude:: /code_examples/synth_flow/opt_01.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.ys``
+   :caption: ``docs/source/code_examples/synth_flow/opt_01.ys``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_01.v
+.. literalinclude:: /code_examples/synth_flow/opt_01.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_01.v``
+   :caption: ``docs/source/code_examples/synth_flow/opt_01.v``
 
 .. figure:: /_images/res/PRESENTATION_ExSyn/opt_02.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.ys
+.. literalinclude:: /code_examples/synth_flow/opt_02.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.ys``
+   :caption: ``docs/source/code_examples/synth_flow/opt_02.ys``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_02.v
+.. literalinclude:: /code_examples/synth_flow/opt_02.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_02.v``
+   :caption: ``docs/source/code_examples/synth_flow/opt_02.v``
 
 .. figure:: /_images/res/PRESENTATION_ExSyn/opt_03.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.ys
+.. literalinclude:: /code_examples/synth_flow/opt_03.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.ys``
+   :caption: ``docs/source/code_examples/synth_flow/opt_03.ys``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_03.v
+.. literalinclude:: /code_examples/synth_flow/opt_03.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_03.v``
+   :caption: ``docs/source/code_examples/synth_flow/opt_03.v``
 
 .. figure:: /_images/res/PRESENTATION_ExSyn/opt_04.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.v
+.. literalinclude:: /code_examples/synth_flow/opt_04.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_04.v``
+   :caption: ``docs/source/code_examples/synth_flow/opt_04.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/opt_04.ys
+.. literalinclude:: /code_examples/synth_flow/opt_04.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/opt_04.ys``
+   :caption: ``docs/source/code_examples/synth_flow/opt_04.ys``
 
 
 When to use :cmd:ref:`opt` or :cmd:ref:`clean`
@@ -249,24 +249,24 @@ Example
 .. figure:: /_images/res/PRESENTATION_ExSyn/memory_01.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.ys
+.. literalinclude:: /code_examples/synth_flow/memory_01.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.ys``
+   :caption: ``docs/source/code_examples/synth_flow/memory_01.ys``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_01.v
+.. literalinclude:: /code_examples/synth_flow/memory_01.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/memory_01.v``
+   :caption: ``docs/source/code_examples/synth_flow/memory_01.v``
 
 .. figure:: /_images/res/PRESENTATION_ExSyn/memory_02.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.v
+.. literalinclude:: /code_examples/synth_flow/memory_02.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/memory_02.v``
+   :caption: ``docs/source/code_examples/synth_flow/memory_02.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/memory_02.ys
+.. literalinclude:: /code_examples/synth_flow/memory_02.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/memory_02.ys``
+   :caption: ``docs/source/code_examples/synth_flow/memory_02.ys``
 
 
 The :cmd:ref:`fsm` command
@@ -321,17 +321,17 @@ The :cmd:ref:`techmap` command
 The :cmd:ref:`techmap` command replaces cells with implementations given as
 verilog source. For example implementing a 32 bit adder using 16 bit adders:
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
+.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01_map.v``
+   :caption: ``docs/source/code_examples/synth_flow/techmap_01_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.v
+.. literalinclude:: /code_examples/synth_flow/techmap_01.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.v``
+   :caption: ``docs/source/code_examples/synth_flow/techmap_01.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.ys
+.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.ys``
+   :caption: ``docs/source/code_examples/synth_flow/techmap_01.ys``
 
 stdcell mapping
 ^^^^^^^^^^^^^^^
@@ -378,13 +378,13 @@ advanced ABC features. It is also possible to write the design with
 Example
 ^^^^^^^
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/abc_01.v
+.. literalinclude:: /code_examples/synth_flow/abc_01.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.v``
+   :caption: ``docs/source/code_examples/synth_flow/abc_01.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/abc_01.ys
+.. literalinclude:: /code_examples/synth_flow/abc_01.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/abc_01.ys``
+   :caption: ``docs/source/code_examples/synth_flow/abc_01.ys``
 
 .. figure:: /_images/res/PRESENTATION_ExSyn/abc_01.*
     :class: width-helper
diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
index 7d4243faf..a16d3cd57 100644
--- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst
+++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst
@@ -18,9 +18,9 @@ A simple circuit
 :numref:`example_v` below provides the Verilog code for a simple circuit which
 we will use to demonstrate the usage of :cmd:ref:`show` in a simple setting.
 
-.. literalinclude:: /APPNOTE_011_Design_Investigation/example.v
+.. literalinclude:: /code_examples/show/example.v
    :language: Verilog
-   :caption: ``docs/source/APPNOTE_011_Design_Investigation/example.v``
+   :caption: ``docs/source/code_examples/show/example.v``
    :name: example_v
 
 The Yosys synthesis script we will be running is included as
@@ -31,7 +31,7 @@ interactive shell to further investigate the circuit before continuing
 synthesis.
 
 .. code-block:: yoscrypt
-   :caption: ``docs/source/APPNOTE_011_Design_Investigation/example.ys``
+   :caption: ``docs/source/code_examples/show/example.ys``
    :name: example_ys
    
    read_verilog example.v
@@ -115,8 +115,8 @@ Break-out boxes for signal vectors
 The code listing below shows a simple circuit which uses a lot of spliced signal
 accesses.
 
-.. literalinclude:: /APPNOTE_011_Design_Investigation/splice.v
-   :caption: ``splice.v``
+.. literalinclude:: /code_examples/show/splice.v
+   :caption: ``docs/source/code_examples/show/splice.v``
    :name: splice_src
 
 Notice how the output for this circuit from the :cmd:ref:`show` command
@@ -341,20 +341,14 @@ a submodule. This has applications in synthesis scripts as well as in reverse
 engineering and analysis.  An example using :cmd:ref:`submod` is shown below for
 reorganizing a module in Yosys and checking the resulting circuit.
 
-.. literalinclude:: ../../../resources/PRESENTATION_ExOth/scrambler.v
+.. literalinclude:: /code_examples/scrambler/scrambler.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExOth/scrambler.v``
+   :caption: ``docs/source/code_examples/scrambler/scrambler.v``
 
-.. code:: yoscrypt
-
-    read_verilog scrambler.v
-
-    hierarchy; proc;;
-
-    cd scrambler
-    submod -name xorshift32 \
-            xs %c %ci %D %c %ci:+[D] %D \
-            %ci*:-$dff xs %co %ci %d
+.. literalinclude:: /code_examples/scrambler/scrambler.ys
+   :language: yoscrypt
+   :caption: ``docs/source/code_examples/scrambler/scrambler.ys``
+   :end-before: cd ..
 
 .. figure:: /_images/res/PRESENTATION_ExOth/scrambler_p01.*
     :class: width-helper
@@ -446,17 +440,13 @@ smaller parts for viewing and working with.  :numref:`submod` does exactly that,
 utilising the :cmd:ref:`submod` command to split the circuit into three
 sections: ``outstage``, ``selstage``, and ``scramble``.
 
-.. code-block:: yoscrypt
-   :caption: The circuit from ``memdemo.v`` broken up using :cmd:ref:`submod`
+.. literalinclude:: /code_examples/selections/submod.ys
+   :language: yoscrypt
+   :caption: Using :cmd:ref:`submod` to break up the circuit from ``memdemo.v``
+   :start-after: cd memdemo
+   :end-at: @selstage
    :name: submod
 
-   select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
-   select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
-   select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
-   submod -name scramble @scramble
-   submod -name outstage @outstage
-   submod -name selstage @selstage
-
 The ``-name`` option is used to specify the name of the new module and also the
 name of the new cell in the current module. The resulting circuits are shown
 below.
@@ -584,7 +574,7 @@ value using the ``-set`` option. (Such a circuit that contains the circuit under
 test plus additional constraint checking circuitry is called a ``miter``
 circuit.)
 
-.. literalinclude:: /APPNOTE_011_Design_Investigation/primetest.v
+.. literalinclude:: /code_examples/primetest.v
    :language: verilog
    :caption: ``primetest.v``, a simple miter circuit for testing if a number is
              prime. But it has a problem.
diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst
index 78b20ea35..b0fcb7b18 100644
--- a/docs/source/using_yosys/more_scripting/selections.rst
+++ b/docs/source/using_yosys/more_scripting/selections.rst
@@ -103,7 +103,7 @@ processed it simply creates the union of all elements on the stack. So
 :yoscrypt:`select t:$add a:foo` will select all ``$add`` cells and all objects
 with the ``foo`` attribute set:   
 
-.. literalinclude:: /APPNOTE_011_Design_Investigation/foobaraddsub.v
+.. literalinclude:: /code_examples/selections/foobaraddsub.v
    :caption: Test module for operations on selections
    :name: foobaraddsub
    :language: verilog
@@ -146,7 +146,7 @@ to set the attribute ``sumstuff`` on all cells generated by the first assign
 statement. (This works on arbitrary large blocks of Verilog code an can be used
 to mark portions of code for analysis.)
 
-.. literalinclude:: /APPNOTE_011_Design_Investigation/sumprod.v
+.. literalinclude:: /code_examples/selections/sumprod.v
    :caption: Another test module for operations on selections
    :name: sumprod
    :language: verilog
@@ -233,7 +233,7 @@ appended to the ``%ci`` action.
 Lets consider :numref:`memdemo_src`. It serves no purpose other than being a
 non-trivial circuit for demonstrating some of the advanced Yosys features. 
 
-.. literalinclude:: /APPNOTE_011_Design_Investigation/memdemo.v
+.. literalinclude:: /code_examples/selections/memdemo.v
    :caption: Demo circuit for demonstrating some advanced Yosys features
    :name: memdemo_src
    :language: verilog
@@ -370,13 +370,13 @@ those cases selection variables must be used to capture more complex selections.
 
 Example:
 
-.. literalinclude:: ../../../resources/PRESENTATION_ExAdv/select.v
+.. literalinclude:: /code_examples/selections/select.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/select.v``
+   :caption: ``docs/source/code_examples/selections/select.v``
 
-.. literalinclude:: ../../../resources/PRESENTATION_ExAdv/select.ys
+.. literalinclude:: /code_examples/selections/select.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExAdv/select.ys``
+   :caption: ``docs/source/code_examples/selections/select.ys``
    :name: select_ys
 
 .. figure:: /_images/res/PRESENTATION_ExAdv/select.*
diff --git a/docs/source/using_yosys/yosys_flows.rst b/docs/source/using_yosys/yosys_flows.rst
index 0bd824b20..88e7a1479 100644
--- a/docs/source/using_yosys/yosys_flows.rst
+++ b/docs/source/using_yosys/yosys_flows.rst
@@ -51,13 +51,13 @@ The extract pass
     
     after `extract`
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test.v
+.. literalinclude:: /code_examples/macc/macc_simple_test.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test.v``
+   :caption: ``docs/source/code_examples/macc/macc_simple_test.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_xmap.v
+.. literalinclude:: /code_examples/macc/macc_simple_xmap.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_xmap.v``
+   :caption: ``docs/source/code_examples/macc/macc_simple_xmap.v``
 
 .. code:: yoscrypt
 
@@ -66,9 +66,9 @@ The extract pass
 
     extract -map macc_simple_xmap.v;;
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_01.v
+.. literalinclude:: /code_examples/macc/macc_simple_test_01.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_01.v``
+   :caption: ``docs/source/code_examples/macc/macc_simple_test_01.v``
 
 .. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01a.*
     :class: width-helper
@@ -76,9 +76,9 @@ The extract pass
 .. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_01b.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_simple_test_02.v
+.. literalinclude:: /code_examples/macc/macc_simple_test_02.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_simple_test_02.v``
+   :caption: ``docs/source/code_examples/macc/macc_simple_test_02.v``
 
 .. figure:: /_images/res/PRESENTATION_ExAdv/macc_simple_test_02a.*
     :class: width-helper
@@ -123,51 +123,51 @@ Make sure ``A`` is the smaller port on all multipliers
 
 .. todo:: add/expand supporting text
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_swap_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_swap_map.v``
+   :caption: ``docs/source/code_examples/macc/macc_xilinx_swap_map.v``
 
 Wrapping multipliers: ``macc_xilinx_wrap_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
    :language: verilog
    :lines: 1-46
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v``
+   :caption: ``docs/source/code_examples/macc/macc_xilinx_wrap_map.v``
 
 Wrapping adders: ``macc_xilinx_wrap_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_wrap_map.v
    :language: verilog
    :lines: 48-89
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v``
+   :caption: ``docs/source/code_examples/macc/macc_xilinx_wrap_map.v``
 
 Extract: ``macc_xilinx_xmap.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_xmap.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_xmap.v``
+   :caption: ``docs/source/code_examples/macc/macc_xilinx_xmap.v``
 
 ... simply use the same wrapping commands on this module as on the design to
 create a template for the :cmd:ref:`extract` command.
 
 Unwrapping multipliers: ``macc_xilinx_unwrap_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
    :language: verilog
    :lines: 1-30
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v``
+   :caption: ``docs/source/code_examples/macc/macc_xilinx_unwrap_map.v``
 
 Unwrapping adders: ``macc_xilinx_unwrap_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_unwrap_map.v
    :language: verilog
    :lines: 32-61
-   :caption: ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_unwrap_map.v``
+   :caption: ``docs/source/code_examples/macc/macc_xilinx_unwrap_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
    :language: verilog
    :lines: 1-6
-   :caption: ``test1`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
+   :caption: ``test1`` of ``docs/source/code_examples/macc/macc_xilinx_test.v``
 
 .. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1a.*
     :class: width-helper
@@ -175,10 +175,10 @@ Unwrapping adders: ``macc_xilinx_unwrap_map.v``
 .. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test1b.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/macc_xilinx_test.v
+.. literalinclude:: /code_examples/macc/macc_xilinx_test.v
    :language: verilog
    :lines: 8-13
-   :caption: ``test2`` of ``docs/resources/PRESENTATION_ExAdv/macc_xilinx_test.v``
+   :caption: ``test2`` of ``docs/source/code_examples/macc/macc_xilinx_test.v``
 
 .. figure:: /_images/res/PRESENTATION_ExAdv/macc_xilinx_test2a.*
     :class: width-helper
@@ -303,17 +303,17 @@ Checking techmap
 
 Remember the following example from :doc:`/getting_started/typical_phases`?
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01_map.v
+.. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01_map.v``
+   :caption: ``docs/source/code_examples/synth_flow/techmap_01_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.v
+.. literalinclude:: /code_examples/synth_flow/techmap_01.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.v``
+   :caption: ``docs/source/code_examples/synth_flow/techmap_01.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExSyn/techmap_01.ys
+.. literalinclude:: /code_examples/synth_flow/techmap_01.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExSyn/techmap_01.ys``
+   :caption: ``docs/source/code_examples/synth_flow/techmap_01.ys``
 
 Lets see if it is correct..
 
@@ -355,22 +355,17 @@ values for ``tready`` that yield the incorrect behavior.
 
 .. todo:: add/expand supporting text
 
-.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_master.v
+.. literalinclude:: /code_examples/axis/axis_master.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExOth/axis_master.v``
+   :caption: ``docs/source/code_examples/axis/axis_master.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExOth/axis_test.v
+.. literalinclude:: /code_examples/axis/axis_test.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExOth/axis_test.v``
+   :caption: ``docs/source/code_examples/axis/axis_test.v``
 
-
-.. code:: yoscrypt
-
-    read_verilog -sv axis_master.v axis_test.v
-    hierarchy -top axis_test
-
-    proc; flatten;;
-    sat -seq 50 -prove-asserts
+.. literalinclude:: /code_examples/axis/axis_test.ys
+   :language: yoscrypt
+   :caption: ``docs/source/code_examples/axis/test.ys``
 
 Result with unmodified ``axis_master.v``:
 
diff --git a/docs/source/yosys_internals/extensions.rst b/docs/source/yosys_internals/extensions.rst
index ec9f2b8d0..06ab9a820 100644
--- a/docs/source/yosys_internals/extensions.rst
+++ b/docs/source/yosys_internals/extensions.rst
@@ -26,22 +26,22 @@ The "stubsnets" example module
 
 The following is the complete code of the "stubsnets" example module. It is
 included in the Yosys source distribution as
-``docs/source/CHAPTER_Prog/stubnets.cc``.
+``docs/source/code_examples/stubnets/stubnets.cc``.
 
-.. literalinclude:: ../CHAPTER_Prog/stubnets.cc
+.. literalinclude:: /code_examples/stubnets/stubnets.cc
     :language: c++
     :linenos:
-    :caption: docs/source/CHAPTER_Prog/stubnets.cc
+    :caption: docs/source/code_examples/stubnets/stubnets.cc
 
-.. literalinclude:: ../CHAPTER_Prog/Makefile
+.. literalinclude:: /code_examples/stubnets/Makefile
     :language: makefile
     :linenos:
-    :caption: docs/source/CHAPTER_Prog/Makefile
+    :caption: docs/source/code_examples/stubnets/Makefile
 
-.. literalinclude:: ../CHAPTER_Prog/test.v
+.. literalinclude:: /code_examples/stubnets/test.v
     :language: verilog
     :linenos:
-    :caption: docs/source/CHAPTER_Prog/test.v
+    :caption: docs/source/code_examples/stubnets/test.v
 
 Quick guide
 -----------
@@ -83,15 +83,13 @@ using these commands.
 Creating modules from scratch
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-.. todo:: add/expand supporting text
+.. todo:: add/expand supporting text, also use files in docs/resources/PRESENTATION_Prog
 
 Let's create the following module using the RTLIL API:
 
-.. code:: Verilog
-
-    module absval(input signed [3:0] a, output [3:0] y);
-        assign y = a[3] ? -a : a;
-    endmodule
+.. literalinclude:: ../../resources/PRESENTATION_Prog/absval_ref.v
+    :language: Verilog
+    :caption: docs/resources/PRESENTATION_Prog/absval_ref.v
 
 .. code:: C++
 
diff --git a/docs/source/yosys_internals/techmap.rst b/docs/source/yosys_internals/techmap.rst
index b89ca9cb9..a2f360a2c 100644
--- a/docs/source/yosys_internals/techmap.rst
+++ b/docs/source/yosys_internals/techmap.rst
@@ -130,20 +130,20 @@ Mapping OR3X1
     This is a simple example for demonstration only.  Techmap shouldn't be used
     to implement basic logic optimization.
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/red_or3x1_map.v
+.. literalinclude:: /code_examples/techmap/red_or3x1_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/red_or3x1_map.v``
+   :caption: ``docs/source/code_examples/techmap/red_or3x1_map.v``
 
 .. figure:: /_images/res/PRESENTATION_ExAdv/red_or3x1.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/red_or3x1_test.ys
+.. literalinclude:: /code_examples/techmap/red_or3x1_test.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExAdv/red_or3x1_test.ys``
+   :caption: ``docs/source/code_examples/techmap/red_or3x1_test.ys``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/red_or3x1_test.v
+.. literalinclude:: /code_examples/techmap/red_or3x1_test.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/red_or3x1_test.v``
+   :caption: ``docs/source/code_examples/techmap/red_or3x1_test.v``
 
 Conditional techmap
 ~~~~~~~~~~~~~~~~~~~
@@ -163,17 +163,17 @@ Example:
 .. figure:: /_images/res/PRESENTATION_ExAdv/sym_mul.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/sym_mul_map.v
+.. literalinclude:: /code_examples/techmap/sym_mul_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/sym_mul_map.v``
+   :caption: ``docs/source/code_examples/techmap/sym_mul_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/sym_mul_test.v
+.. literalinclude:: /code_examples/techmap/sym_mul_test.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/sym_mul_test.v``
+   :caption: ``docs/source/code_examples/techmap/sym_mul_test.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/sym_mul_test.ys
+.. literalinclude:: /code_examples/techmap/sym_mul_test.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExAdv/sym_mul_test.ys``
+   :caption: ``docs/source/code_examples/techmap/sym_mul_test.ys``
 
 
 Scripting in map modules
@@ -202,17 +202,17 @@ Example:
 .. figure:: /_images/res/PRESENTATION_ExAdv/mymul.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/mymul_map.v
+.. literalinclude:: /code_examples/techmap/mymul_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/mymul_map.v``
+   :caption: ``docs/source/code_examples/techmap/mymul_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/mymul_test.v
+.. literalinclude:: /code_examples/techmap/mymul_test.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/mymul_test.v``
+   :caption: ``docs/source/code_examples/techmap/mymul_test.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/mymul_test.ys
+.. literalinclude:: /code_examples/techmap/mymul_test.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExAdv/mymul_test.ys``
+   :caption: ``docs/source/code_examples/techmap/mymul_test.ys``
 
 Handling constant inputs
 ~~~~~~~~~~~~~~~~~~~~~~~~
@@ -232,17 +232,17 @@ Example:
 .. figure:: /_images/res/PRESENTATION_ExAdv/mulshift.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/mulshift_map.v
+.. literalinclude:: /code_examples/techmap/mulshift_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/mulshift_map.v``
+   :caption: ``docs/source/code_examples/techmap/mulshift_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/mulshift_test.v
+.. literalinclude:: /code_examples/techmap/mulshift_test.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/mulshift_test.v``
+   :caption: ``docs/source/code_examples/techmap/mulshift_test.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/mulshift_test.ys
+.. literalinclude:: /code_examples/techmap/mulshift_test.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExAdv/mulshift_test.ys``
+   :caption: ``docs/source/code_examples/techmap/mulshift_test.ys``
 
 Handling shorted inputs
 ~~~~~~~~~~~~~~~~~~~~~~~
@@ -263,17 +263,17 @@ Example:
 .. figure:: /_images/res/PRESENTATION_ExAdv/addshift.*
     :class: width-helper
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/addshift_map.v
+.. literalinclude:: /code_examples/techmap/addshift_map.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/addshift_map.v``
+   :caption: ``docs/source/code_examples/techmap/addshift_map.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/addshift_test.v
+.. literalinclude:: /code_examples/techmap/addshift_test.v
    :language: verilog
-   :caption: ``docs/resources/PRESENTATION_ExAdv/addshift_test.v``
+   :caption: ``docs/source/code_examples/techmap/addshift_test.v``
 
-.. literalinclude:: ../../resources/PRESENTATION_ExAdv/addshift_test.ys
+.. literalinclude:: /code_examples/techmap/addshift_test.ys
    :language: yoscrypt
-   :caption: ``docs/resources/PRESENTATION_ExAdv/addshift_test.ys``
+   :caption: ``docs/source/code_examples/techmap/addshift_test.ys``
 
 Notes on using techmap
 ~~~~~~~~~~~~~~~~~~~~~~