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https://github.com/YosysHQ/yosys
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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
20 lines
332 B
Verilog
20 lines
332 B
Verilog
module memdemo(clk, d, y);
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input clk;
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input [3:0] d;
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output reg [3:0] y;
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integer i;
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reg [1:0] s1, s2;
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reg [3:0] mem [0:3];
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always @(posedge clk) begin
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for (i = 0; i < 4; i = i+1)
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mem[i] <= mem[(i+1) % 4] + mem[(i+2) % 4];
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{ s2, s1 } = d ? { s1, s2 } ^ d : 4'b0;
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mem[s1] <= d;
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y <= mem[s2];
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end
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endmodule
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