mirror of
https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
6 lines
138 B
Plaintext
6 lines
138 B
Plaintext
read_verilog abc_01.v
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read_verilog -lib abc_01_cells.v
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hierarchy -check -top test
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proc; opt; techmap
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abc -dff -liberty abc_01_cells.lib;;
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