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https://github.com/YosysHQ/yosys
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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
9 lines
240 B
Verilog
9 lines
240 B
Verilog
module foobaraddsub(a, b, c, d, fa, fs, ba, bs);
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input [7:0] a, b, c, d;
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output [7:0] fa, fs, ba, bs;
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assign fa = a + (* foo *) b;
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assign fs = a - (* foo *) b;
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assign ba = c + (* bar *) d;
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assign bs = c - (* bar *) d;
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endmodule
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