mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-14 12:58:45 +00:00
dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
24 lines
733 B
Makefile
24 lines
733 B
Makefile
PROGRAM_PREFIX :=
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YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
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EXAMPLE = example_00 example_01 example_02 example_03
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EXAMPLE_DOTS := $(addsuffix .dot,$(EXAMPLE))
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CMOS = cmos_00 cmos_01
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CMOS_DOTS := $(addsuffix .dot,$(CMOS))
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all: splice.dot $(EXAMPLE_DOTS) $(CMOS_DOTS)
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splice.dot: splice.v
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$(YOSYS) -p 'proc; opt; show -format dot -prefix splice' splice.v
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$(EXAMPLE_DOTS): example.v example.ys
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$(YOSYS) example.ys
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cmos_00.dot: cmos.v
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$(YOSYS) -p 'read_verilog cmos.v; techmap; abc -liberty ../intro/mycells.lib;; show -format dot -prefix cmos_00'
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cmos_01.dot: cmos.v
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$(YOSYS) -p 'read_verilog cmos.v; techmap; splitnets -ports; abc -liberty ../intro/mycells.lib;; show -lib ../intro/mycells.v -format dot -prefix cmos_01'
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