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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
13 lines
190 B
Verilog
13 lines
190 B
Verilog
module counter (clk, rst, en, count);
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input clk, rst, en;
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output reg [1:0] count;
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always @(posedge clk)
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if (rst)
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count <= 2'd0;
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else if (en)
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count <= count + 2'd1;
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endmodule
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