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https://github.com/YosysHQ/yosys
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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
20 lines
271 B
Verilog
20 lines
271 B
Verilog
module test(input CLK, ARST,
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output [7:0] Q1, Q2, Q3);
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wire NO_CLK = 0;
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always @(posedge CLK, posedge ARST)
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if (ARST)
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Q1 <= 42;
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always @(posedge NO_CLK, posedge ARST)
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if (ARST)
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Q2 <= 42;
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else
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Q2 <= 23;
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always @(posedge CLK)
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Q3 <= 42;
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endmodule
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