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https://github.com/YosysHQ/yosys
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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
16 lines
308 B
Verilog
16 lines
308 B
Verilog
module test(clk, s, a, y);
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input clk, s;
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input [15:0] a;
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output [15:0] y;
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reg [15:0] b, c;
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always @(posedge clk) begin
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b <= a;
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c <= b;
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end
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wire [15:0] state_a = (a ^ b) + c;
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wire [15:0] state_b = (a ^ b) - c;
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assign y = !s ? state_a : state_b;
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endmodule
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