mirror of
https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
17 lines
521 B
Plaintext
17 lines
521 B
Plaintext
read_verilog memdemo.v
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proc; opt; memory; opt
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cd memdemo
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select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff
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select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d
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select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
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submod -name scramble @scramble
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submod -name outstage @outstage
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submod -name selstage @selstage
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cd ..
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show -format dot -prefix submod_00 memdemo
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show -format dot -prefix submod_01 scramble
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show -format dot -prefix submod_02 outstage
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show -format dot -prefix submod_03 selstage
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