mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
23 lines
391 B
Plaintext
23 lines
391 B
Plaintext
read_verilog scrambler.v
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hierarchy; proc;;
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cd scrambler
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submod -name xorshift32 xs %c %ci %D %c %ci:+[D] %D %ci*:-$dff xs %co %ci %d
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cd ..
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show -prefix scrambler_p01 -format dot -notitle scrambler
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show -prefix scrambler_p02 -format dot -notitle xorshift32
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echo on
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cd xorshift32
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rename n2 in
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rename n1 out
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eval -set in 1 -show out
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eval -set in 270369 -show out
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sat -set out 632435482
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