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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
13 lines
177 B
Verilog
13 lines
177 B
Verilog
module sumprod(a, b, c, sum, prod);
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input [7:0] a, b, c;
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output [7:0] sum, prod;
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{* sumstuff *}
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assign sum = a + b + c;
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{* *}
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assign prod = a * b * c;
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endmodule
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