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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
11 lines
130 B
Verilog
11 lines
130 B
Verilog
module DSP48_MACC (a, b, c, y);
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input [17:0] a;
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input [24:0] b;
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input [47:0] c;
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output [47:0] y;
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assign y = a*b + c;
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endmodule
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