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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
11 lines
212 B
Verilog
11 lines
212 B
Verilog
module splice_demo(a, b, c, d, e, f, x, y);
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input [1:0] a, b, c, d, e, f;
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output [1:0] x = {a[0], a[1]};
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output [11:0] y;
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assign {y[11:4], y[1:0], y[3:2]} =
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{a, b, -{c, d}, ~{e, f}};
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endmodule
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