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https://github.com/YosysHQ/yosys
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dbc38d72cf
Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
11 lines
168 B
Verilog
11 lines
168 B
Verilog
module test(input clk, a, b, c,
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output reg y);
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reg [2:0] q1, q2;
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always @(posedge clk) begin
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q1 <= { a, b, c };
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q2 <= q1;
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y <= ^q2;
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end
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endmodule
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