mirror of
https://github.com/YosysHQ/yosys
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Code now resides in `docs/source/code_examples`. `CHAPTER_Prog` -> `stubnets` `APPNOTE_011_Design_Investigation` -> `selections` and `show` `resources/PRESENTATION_Intro` -> `intro` `resources/PRESENTATION_ExSyn` -> `synth_flow` `resources/PRESENTATION_ExAdv` -> `techmap`, `macc`, and `selections` `resources/PRESENTATION_ExOth` -> `scrambler` and `axis` Note that generated images are not yet configured to build from the new code locations.
12 lines
203 B
Plaintext
12 lines
203 B
Plaintext
read_verilog example.v
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show -format dot -prefix example_00
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proc
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show -format dot -prefix example_01
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opt
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show -format dot -prefix example_02
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cd example
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select t:$add
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show -format dot -prefix example_03
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