Scott Ashcroft
518986d45c
Make cxxrtl tests work on 32-bit by using __builtin_clzll when needed
2025-03-25 13:12:04 +00:00
Krystine Sherwin
0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY
...
Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
2025-03-25 12:15:54 +13:00
KrystalDelusion
a647731812
Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing
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opt_merge: hashing performance and correctness
2025-03-25 10:36:02 +13:00
Akash Levy
95f489beec
Merge nice gzip refactor
2025-03-20 16:47:12 -07:00
Emil J. Tywoniak
980a0a15c1
stat: allow gzipped liberty files
2025-03-19 13:43:44 +01:00
Anhijkt
5ae32efca5
ice40_dsp: add test
2025-03-15 20:05:57 +02:00
Akash Levy
1c0d4a43b3
Merge branch 'YosysHQ:main' into main
2025-03-14 18:07:55 -07:00
KrystalDelusion
9f1271bee0
Merge pull request #4922 from Anhijkt/fix-splitcells-assert
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splitcells: Fix the assertion bug caused by out-of-bound offset
2025-03-14 16:52:38 +13:00
Krystine Sherwin
8405b3b723
select: Fix -none and -clear
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If the selection stack only has one element (which it normally does), then
`design->pop_selection()` automatically resets to the default full selection.
This is a problem for `select [-none | -clear]` which were trying to replace the
current selection, but because the pop added an extra element when the `execute`
returned, the extra selection (the one we actually wanted) gets popped too. So
instead, reassign `design->selection()` in the same way as if we called `select
[selection]`.
Also adds selection stack tests, and removes the accidentally-committed
`boxes_dummy.ys`.
2025-03-14 16:32:18 +13:00
Krystine Sherwin
9a9cd05f6c
tests: Fixes for boxes
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cxxrtl `test_unconnected_output` and simple_abc9 `abc9.v` both expect boxed modules in the outputs, so make sure they work as expected.
2025-03-14 14:08:15 +13:00
Krystine Sherwin
061c234559
tests/select: Add tests for selections with boxes
2025-03-14 14:05:40 +13:00
Alain Dargelas
68312d046a
Fix Yosys test failures
2025-03-13 14:15:13 -07:00
Akash Levy
6f818af110
Ignore test collateral
2025-03-13 01:55:22 -07:00
Akash Levy
0a68eb32b3
Disable sub-neg peepopt
2025-03-13 01:55:14 -07:00
Akash Levy
e4066b784d
Merge remote-tracking branch 'upstream/main'
2025-03-12 19:21:32 -07:00
Martin Povišer
6da543a61a
Merge pull request #4818 from povik/macc_v2
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Add `$macc_v2`
2025-03-12 22:55:40 +01:00
Akash Levy
4d4e574ebb
Merge pull request #60 from alaindargelas/peepopt_neg_sub
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neg-sub peepopt pass
2025-03-10 15:48:49 -07:00
Alain Dargelas
e1671b45b6
Code review
2025-03-10 14:44:14 -07:00
Akash Levy
e360511339
Merge branch 'YosysHQ:main' into main
2025-03-10 14:21:49 -07:00
Alain Dargelas
6de80bc6b3
neg sub pass
2025-03-10 13:47:06 -07:00
Anhijkt
be3dfdc5ad
splitcells: add tests
2025-03-10 19:41:22 +02:00
Martin Povišer
d8a4991289
Merge pull request #4931 from povik/buf-clean
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opt_clean, simplemap: Add `$buf` handling
2025-03-10 15:10:17 +01:00
Emil J. Tywoniak
33bfc9d19c
opt_merge: test more kinds of cells
2025-03-10 13:14:06 +01:00
Emil J. Tywoniak
ae7a97cc2d
opt_merge: test some unary cells
2025-03-10 13:14:06 +01:00
Emil J. Tywoniak
176faae7c9
opt_merge: fix trivial binary regression
2025-03-10 13:14:06 +01:00
Martin Povišer
557047fe1e
opt_clean, simplemap: Add $buf handling
2025-03-07 16:08:38 +01:00
Akash Levy
fa97c4830e
Generalize muxadd to muxorder
2025-03-06 16:57:47 -08:00
Akash Levy
881080a827
Merge upstream
2025-03-05 07:54:26 -08:00
N. Engelhardt
268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff
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add IOFF inference for qlf_k6n10f
2025-03-03 14:12:09 +00:00
Akash Levy
9d3b7f7474
Merge branch 'YosysHQ:main' into main
2025-02-26 09:51:44 -08:00
Emil J
b4a169527d
Merge pull request #4894 from YosysHQ/emil/abstract
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Add `abstract` pass for formal verification
2025-02-25 11:16:37 +01:00
Emil J. Tywoniak
3f60a2cc67
abstract: test -slice from:to for -init
2025-02-25 00:22:14 +01:00
Emil J. Tywoniak
3cb7054e53
abstract: test -slice for all modes, -rtlilslice for -init
2025-02-25 00:18:16 +01:00
Emil J. Tywoniak
5bd18613bb
abstract: test -init
2025-02-19 23:03:43 +01:00
Alain Dargelas
929c817384
splitnets new options
2025-02-19 09:43:53 -08:00
Emil J. Tywoniak
34e3fcbb31
abstract: test -value
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
d3a90021ad
abstract: test -state
2025-02-18 17:08:45 +01:00
Jannis Harder
7cd822b7f5
rtlil: Add {from,to}_hdl_index methods to Wire
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In the past we had the occasional bug due to some place not handling all
4 combinations of upto/downto and zero/nonzero start_offset correctly.
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
387d0de383
abstract: -state allow partial abstraction, don't use buffer-normalized mode
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
6027030215
abstract: -value MVP, use buffer-normalized mode
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
4637fa74e3
abstract: -init MVP
2025-02-18 17:08:45 +01:00
Emil J. Tywoniak
e4ca7b8846
abstract: -state MVP
2025-02-18 17:08:45 +01:00
Akash Levy
33c72b0f25
Merge branch 'YosysHQ:main' into main
2025-02-15 15:54:28 -08:00
Akash Levy
c4254a9a95
Final cleanup
2025-02-14 10:18:13 -08:00
Akash Levy
1b13b5d6ea
Move segv and reenable loops.v test
2025-02-14 10:02:30 -08:00
Akash Levy
fd811ddaee
Cleanup
2025-02-14 08:48:27 -08:00
Akash Levy
9cc82c7044
Revert clocking.ys
2025-02-13 20:32:17 -08:00
Akash Levy
c8c97ea00b
Revert back to using Verific naming
2025-02-13 19:40:33 -08:00
Krystine Sherwin
db5b76edc1
Add test for shifting by INT_MAX
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Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
2025-02-14 14:01:27 +13:00
Akash Levy
4e45a86e12
Merge branch 'YosysHQ:main' into main
2025-02-06 12:29:43 -08:00
