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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-02-15 15:54:28 -08:00 • committed by GitHub
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9
tests/opt/opt_expr_shr_int_max.ys Normal file
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read_verilog << EOF
module uut_00034(b, y);
input signed [30:0] b;
output [11:0] y = b >> ~31'b0; // shift by INT_MAX
endmodule
EOF
# This should succeed, even with UBSAN halt_on_error
opt_expr