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Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing
opt_merge: hashing performance and correctness
This commit is contained in:
KrystalDelusion
GitHub
commit
a647731812
2 changed files with 312 additions and 115 deletions
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@ -26,6 +26,8 @@
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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#include <unordered_map>
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#include <array>
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USING_YOSYS_NAMESPACE
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@ -42,6 +44,22 @@ struct OptMergeWorker
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CellTypes ct;
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int total_count;
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static vector<pair<SigBit, SigSpec>> sorted_pmux_in(const dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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SigSpec sig_s = conn.at(ID::S);
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SigSpec sig_b = conn.at(ID::B);
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int s_width = GetSize(sig_s);
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int width = GetSize(sig_b) / s_width;
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vector<pair<SigBit, SigSpec>> sb_pairs;
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for (int i = 0; i < s_width; i++)
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sb_pairs.push_back(pair<SigBit, SigSpec>(sig_s[i], sig_b.extract(i*width, width)));
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std::sort(sb_pairs.begin(), sb_pairs.end());
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return sb_pairs;
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}
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static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
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{
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SigSpec sig_s = conn.at(ID::S);
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@ -65,95 +83,78 @@ struct OptMergeWorker
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}
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}
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std::string int_to_hash_string(unsigned int v)
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Hasher hash_cell_inputs(const RTLIL::Cell *cell, Hasher h) const
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{
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if (v == 0)
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return "0";
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std::string str = "";
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while (v > 0) {
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str += 'a' + (v & 15);
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v = v >> 4;
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}
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return str;
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}
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uint64_t hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
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{
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vector<string> hash_conn_strings;
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std::string hash_string = cell->type.str() + "\n";
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const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
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// TODO: when implemented, use celltypes to match:
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// (builtin || stdcell) && (unary || binary) && symmetrical
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
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ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
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alt_conn = *conn;
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if (assign_map(alt_conn.at(ID::A)) < assign_map(alt_conn.at(ID::B))) {
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alt_conn[ID::A] = conn->at(ID::B);
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alt_conn[ID::B] = conn->at(ID::A);
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std::array<RTLIL::SigSpec, 2> inputs = {
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assign_map(cell->getPort(ID::A)),
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assign_map(cell->getPort(ID::B))
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};
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std::sort(inputs.begin(), inputs.end());
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h = hash_ops<std::array<RTLIL::SigSpec, 2>>::hash_into(inputs, h);
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} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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SigSpec a = assign_map(cell->getPort(ID::A));
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a.sort();
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h = a.hash_into(h);
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} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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SigSpec a = assign_map(cell->getPort(ID::A));
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a.sort_and_unify();
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h = a.hash_into(h);
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} else if (cell->type == ID($pmux)) {
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dict<RTLIL::IdString, RTLIL::SigSpec> conn = cell->connections();
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assign_map.apply(conn.at(ID::A));
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assign_map.apply(conn.at(ID::B));
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assign_map.apply(conn.at(ID::S));
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for (const auto& [s_bit, b_chunk] : sorted_pmux_in(conn)) {
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h = s_bit.hash_into(h);
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h = b_chunk.hash_into(h);
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}
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conn = &alt_conn;
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} else
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if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at(ID::A));
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alt_conn.at(ID::A).sort();
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conn = &alt_conn;
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} else
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if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at(ID::A));
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alt_conn.at(ID::A).sort_and_unify();
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conn = &alt_conn;
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} else
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if (cell->type == ID($pmux)) {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at(ID::A));
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assign_map.apply(alt_conn.at(ID::B));
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assign_map.apply(alt_conn.at(ID::S));
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sort_pmux_conn(alt_conn);
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conn = &alt_conn;
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}
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for (auto &it : *conn) {
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RTLIL::SigSpec sig;
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if (cell->output(it.first)) {
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if (it.first == ID::Q && RTLIL::builtin_ff_cell_types().count(cell->type)) {
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// For the 'Q' output of state elements,
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// use its (* init *) attribute value
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sig = initvals(it.second);
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h = assign_map(cell->getPort(ID::A)).hash_into(h);
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} else {
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std::vector<std::pair<IdString, SigSpec>> conns;
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for (const auto& conn : cell->connections()) {
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conns.push_back(conn);
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}
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std::sort(conns.begin(), conns.end());
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for (const auto& [port, sig] : conns) {
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if (!cell->output(port)) {
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h = port.hash_into(h);
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h = assign_map(sig).hash_into(h);
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}
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else
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continue;
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}
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else
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sig = assign_map(it.second);
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string s = "C " + it.first.str() + "=";
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for (auto &chunk : sig.chunks()) {
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if (chunk.wire)
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s += "{" + chunk.wire->name.str() + " " +
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int_to_hash_string(chunk.offset) + " " +
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int_to_hash_string(chunk.width) + "}";
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else
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s += RTLIL::Const(chunk.data).as_string();
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}
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hash_conn_strings.push_back(s + "\n");
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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h = initvals(cell->getPort(ID::Q)).hash_into(h);
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}
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for (auto &it : cell->parameters)
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hash_conn_strings.push_back("P " + it.first.str() + "=" + it.second.as_string() + "\n");
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std::sort(hash_conn_strings.begin(), hash_conn_strings.end());
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for (auto it : hash_conn_strings)
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hash_string += it;
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return std::hash<std::string>{}(hash_string);
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return h;
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}
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
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static Hasher hash_cell_parameters(const RTLIL::Cell *cell, Hasher h)
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{
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log_assert(cell1 != cell2);
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using Paramvec = std::vector<std::pair<IdString, Const>>;
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Paramvec params;
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for (const auto& param : cell->parameters) {
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params.push_back(param);
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}
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std::sort(params.begin(), params.end());
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return hash_ops<Paramvec>::hash_into(params, h);
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}
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Hasher hash_cell_function(const RTLIL::Cell *cell, Hasher h) const
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{
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h.eat(cell->type);
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h = hash_cell_inputs(cell, h);
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h = hash_cell_parameters(cell, h);
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return h;
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}
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const
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{
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if (cell1 == cell2) return true;
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if (cell1->type != cell2->type) return false;
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if (cell1->parameters != cell2->parameters)
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@ -252,21 +253,51 @@ struct OptMergeWorker
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initvals.set(&assign_map, module);
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bool did_something = true;
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// A cell may have to go through a lot of collisions if the hash
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// function is performing poorly, but it's a symptom of something bad
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// beyond the user's control.
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while (did_something)
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{
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells_.size());
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for (auto &it : module->cells_) {
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if (!design->selected(module, it.second))
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cells.reserve(module->cells().size());
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for (auto cell : module->cells()) {
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if (!design->selected(module, cell))
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continue;
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if (mode_keepdc && has_dont_care_initval(it.second))
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if (cell->type.in(ID($meminit), ID($meminit_v2), ID($mem), ID($mem_v2))) {
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// Ignore those for performance: meminit can have an excessively large port,
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// mem can have an excessively large parameter holding the init data
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continue;
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if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known()))
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cells.push_back(it.second);
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}
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if (mode_keepdc && has_dont_care_initval(cell))
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continue;
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if (ct.cell_known(cell->type) || (mode_share_all && cell->known()))
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cells.push_back(cell);
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}
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did_something = false;
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dict<uint64_t, RTLIL::Cell*> sharemap;
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// We keep a set of known cells. They're hashed with our hash_cell_function
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// and compared with our compare_cell_parameters_and_connections.
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// Both need to capture OptMergeWorker to access initvals
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struct CellPtrHash {
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const OptMergeWorker& worker;
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CellPtrHash(const OptMergeWorker& w) : worker(w) {}
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std::size_t operator()(const Cell* c) const {
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return (std::size_t)worker.hash_cell_function(c, Hasher()).yield();
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}
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};
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struct CellPtrEqual {
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const OptMergeWorker& worker;
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CellPtrEqual(const OptMergeWorker& w) : worker(w) {}
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bool operator()(const Cell* lhs, const Cell* rhs) const {
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return worker.compare_cell_parameters_and_connections(lhs, rhs);
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}
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};
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std::unordered_set<
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RTLIL::Cell*,
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CellPtrHash,
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CellPtrEqual> known_cells (0, CellPtrHash(*this), CellPtrEqual(*this));
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for (auto cell : cells)
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{
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if ((!mode_share_all && !ct.cell_known(cell->type)) || !cell->known())
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@ -275,36 +306,36 @@ struct OptMergeWorker
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if (cell->type == ID($scopeinfo))
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continue;
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uint64_t hash = hash_cell_parameters_and_connections(cell);
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auto r = sharemap.insert(std::make_pair(hash, cell));
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if (!r.second) {
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if (compare_cell_parameters_and_connections(cell, r.first->second)) {
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if (cell->has_keep_attr()) {
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if (r.first->second->has_keep_attr())
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continue;
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std::swap(r.first->second, cell);
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}
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did_something = true;
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log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), r.first->second->name.c_str());
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for (auto &it : cell->connections()) {
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if (cell->output(it.first)) {
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RTLIL::SigSpec other_sig = r.first->second->getPort(it.first);
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log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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Const init = initvals(other_sig);
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initvals.remove_init(it.second);
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initvals.remove_init(other_sig);
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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initvals.set_init(other_sig, init);
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}
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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module->remove(cell);
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total_count++;
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auto [cell_in_map, inserted] = known_cells.insert(cell);
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if (!inserted) {
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// We've failed to insert since we already have an equivalent cell
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Cell* other_cell = *cell_in_map;
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if (cell->has_keep_attr()) {
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if (other_cell->has_keep_attr())
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continue;
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known_cells.erase(other_cell);
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known_cells.insert(cell);
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std::swap(other_cell, cell);
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}
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did_something = true;
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log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), other_cell->name.c_str());
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for (auto &it : cell->connections()) {
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if (cell->output(it.first)) {
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RTLIL::SigSpec other_sig = other_cell->getPort(it.first);
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log_debug(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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Const init = initvals(other_sig);
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initvals.remove_init(it.second);
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initvals.remove_init(other_sig);
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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initvals.set_init(other_sig, init);
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}
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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module->remove(cell);
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total_count++;
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}
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}
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}
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166
tests/opt/opt_merge_basic.ys
Normal file
166
tests/opt/opt_merge_basic.ys
Normal file
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@ -0,0 +1,166 @@
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read_verilog <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output [7:0] X, Y;
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assign X = A + B;
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assign Y = A + B;
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endmodule
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EOT
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# Most basic case
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# Binary
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select -assert-count 2 t:$add
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module top(A, B, C, X, Y);
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input [7:0] A, B, C;
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output [7:0] X, Y;
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assign X = A + B;
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assign Y = A + C; // <- look here
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endmodule
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EOT
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# Reject on a different input
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select -assert-count 2 t:$add
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opt_merge
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select -assert-count 2 t:$add
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design -reset
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read_verilog <<EOT
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module top(A, X, Y);
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input [7:0] A;
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output X, Y;
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assign X = ^A;
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assign Y = ^A;
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endmodule
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EOT
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# Unary
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select -assert-count 2 t:$reduce_xor
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dump
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opt_merge
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select -assert-count 1 t:$reduce_xor
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design -reset
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read_verilog -icells <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output X, Y;
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\$reduce_xor #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd16),
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.Y_WIDTH(32'd1),
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) one (
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.A({A, B}), // <- look here
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.Y(X)
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);
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\$reduce_xor #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd16),
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.Y_WIDTH(32'd1),
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) other (
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.A({B, A}), // <- look here
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.Y(Y)
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);
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endmodule
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EOT
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# Unary is sorted
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opt_expr
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select -assert-count 2 t:$reduce_xor
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$reduce_xor
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design -reset
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read_verilog -icells <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output X, Y;
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\$reduce_or #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd24),
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.Y_WIDTH(32'd1),
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) one (
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.A({A, B, B}), // <- look here
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.Y(X)
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);
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\$reduce_or #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd24),
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.Y_WIDTH(32'd1),
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) other (
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.A({A, A, B}), // <- look here
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.Y(Y)
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);
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endmodule
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EOT
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# Unary is unified when valid
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opt_expr
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select -assert-count 2 t:$reduce_or
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equiv_opt -assert opt_merge
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design -load postopt
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select -assert-count 1 t:$reduce_or
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design -reset
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read_verilog -icells <<EOT
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module top(A, B, X, Y);
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input [7:0] A, B;
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output X, Y;
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\$reduce_xor #(
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.A_SIGNED(32'd0),
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.A_WIDTH(32'd24),
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.Y_WIDTH(32'd1),
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) one (
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.A({A, B, B}), // <- look here
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.Y(X)
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);
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\$reduce_xor #(
|
||||
.A_SIGNED(32'd0),
|
||||
.A_WIDTH(32'd24),
|
||||
.Y_WIDTH(32'd1),
|
||||
) other (
|
||||
.A({A, A, B}), // <- look here
|
||||
.Y(Y)
|
||||
);
|
||||
endmodule
|
||||
EOT
|
||||
# Unary isn't unified when that would be invalid
|
||||
opt_expr
|
||||
select -assert-count 2 t:$reduce_xor
|
||||
equiv_opt -assert opt_merge
|
||||
design -load postopt
|
||||
select -assert-count 2 t:$reduce_xor
|
||||
|
||||
# TODO pmux
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top(A, B, X, Y);
|
||||
input [7:0] A, B;
|
||||
output X, Y;
|
||||
assign X = A > B;
|
||||
assign Y = A > B;
|
||||
endmodule
|
||||
EOT
|
||||
# Exercise the general case in hash_cell_inputs - accept
|
||||
opt_expr
|
||||
select -assert-count 2 t:$gt
|
||||
equiv_opt -assert opt_merge
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$gt
|
||||
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top(A, B, C, X, Y);
|
||||
input [7:0] A, B, C;
|
||||
output X, Y;
|
||||
assign X = A > B;
|
||||
assign Y = A > C; // <- look here
|
||||
endmodule
|
||||
EOT
|
||||
# Exercise the general case in hash_cell_inputs - reject
|
||||
opt_expr
|
||||
select -assert-count 2 t:$gt
|
||||
opt_merge
|
||||
select -assert-count 2 t:$gt
|
||||
Loading…
Add table
Add a link
Reference in a new issue