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Revert back to using Verific naming

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This commit is contained in:
Akash Levy 2025-02-13 19:40:33 -08:00
parent aa515e8847
commit c8c97ea00b
10 changed files with 75 additions and 123 deletions
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6
tests/verific/blackbox.ys.DISABLED
View file

@ -1,4 +1,4 @@
import -sv -lib <<EOF
verific -sv -lib <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
always @(posedge clk) begin
@ -11,14 +11,14 @@ end
endmodule
EOF
import -sv <<EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
import -import top
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL

6
tests/verific/blackbox_empty.ys.DISABLED
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@ -1,17 +1,17 @@
import -sv <<EOF
verific -sv <<EOF
module TEST_CELL(input clk, input a, input b, output reg c);
parameter PATH = "DEFAULT";
endmodule
EOF
import -sv <<EOF
verific -sv <<EOF
module top(input clk, input a, input b, output c, output d);
TEST_CELL #(.PATH("TEST")) test1(.clk(clk),.a(a),.b(1'b1),.c(c));
TEST_CELL #(.PATH("DEFAULT")) test2(.clk(clk),.a(a),.b(1'bx),.c(d));
endmodule
EOF
import -import top
verific -import top
hierarchy -top top
stat
select -assert-count 2 t:TEST_CELL

6
tests/verific/blackbox_ql.ys.DISABLED
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@ -1,6 +1,6 @@
import -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
verific -sv -lib +/quicklogic/qlf_k6n10f/dsp_sim.v
import -sv <<EOF
verific -sv <<EOF
module top (
input wire [19:0] a,
input wire [17:0] b,
@ -35,7 +35,7 @@ endmodule
EOF
import -import top
verific -import top
hierarchy -top top
synth_quicklogic -family qlf_k6n10f
select -assert-count 1 t:QL_DSP2_MULT_REGIN_REGOUT a:MODE_BITS=80'h1232324

8
tests/verific/case.ys
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@ -1,12 +1,12 @@
import -cfg db_abstract_case_statement_synthesis 0
verific -cfg db_abstract_case_statement_synthesis 0
read -sv case.sv
import -import top
verific -import top
prep
rename top gold
import -cfg db_abstract_case_statement_synthesis 1
verific -cfg db_abstract_case_statement_synthesis 1
read -sv case.sv
import -import top
verific -import top
prep
rename top gate

2
tests/verific/clocking.ys
View file

@ -4,7 +4,7 @@ always @(*) assert(foo);
endmodule
EOT
import -import test
verific -import test
prep
select -assert-count 1 t:$assert

2
tests/verific/memory_semantics.ys.DISABLED
View file

@ -1,4 +1,4 @@
import -formal <<EOF
verific -formal <<EOF
module top(clk);
input wire clk;

8
tests/verific/range_case.ys
View file

@ -1,12 +1,12 @@
import -cfg db_abstract_case_statement_synthesis 0
verific -cfg db_abstract_case_statement_synthesis 0
read -sv range_case.sv
import -import top
verific -import top
proc
rename top gold
import -cfg db_abstract_case_statement_synthesis 1
verific -cfg db_abstract_case_statement_synthesis 1
read -sv range_case.sv
import -import top
verific -import top
proc
rename top gate

4
tests/verific/rom_case.ys.DISABLED
View file

@ -1,4 +1,4 @@
import -sv <<EOF
verific -sv <<EOF
module rom(input clk, input [2:0] addr, (* ram_style = "block" *) output reg [7:0] data);
always @(posedge clk) begin
@ -30,7 +30,7 @@ select -assert-count 1 t:RAM_BLOCK_SDP
design -reset
import -vhdl <<EOF
verific -vhdl <<EOF
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

4
tests/verific/setenv.ys
View file

@ -1,4 +1,4 @@
setenv filename case.sv
import -f -sv setenv.flist
import -import top
verific -f -sv setenv.flist
verific -import top
select -assert-mod-count 1 top