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Cleanup

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This commit is contained in:
Akash Levy 2025-02-14 08:48:27 -08:00
parent f76fd9280b
commit fd811ddaee
23 changed files with 39 additions and 126 deletions
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45
tests/liberty/busdef2.lib
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/* Tests two things: */
/* (1) Bus without any individual pin definition */
/* (2) Having a custom field with define, which can allow square brackets */
library (liberty_define) {
delay_model : "table_lookup" ;
simulation : false ;
capacitive_load_unit (1,pF) ;
leakage_power_unit : "1pW" ;
current_unit : "1A" ;
pulling_resistance_unit : "1kohm" ;
time_unit : "1ns" ;
voltage_unit : "1v" ;
library_features : "report_delay_calculation" ;
input_threshold_pct_rise : 50 ;
input_threshold_pct_fall : 50 ;
output_threshold_pct_rise : 50 ;
output_threshold_pct_fall : 50 ;
slew_lower_threshold_pct_rise : 30 ;
slew_lower_threshold_pct_fall : 30 ;
slew_upper_threshold_pct_rise : 70 ;
slew_upper_threshold_pct_fall : 70 ;
slew_derate_from_library : 1.0 ;
nom_process : 1.0 ;
nom_temperature : 85.0 ;
nom_voltage : 0.75 ;
type (bus8) {
base_type : "array";
data_type : "bit";
bit_width : 8;
bit_from : 7;
bit_to : 0;
}
define (original_pin, pin, string) ;
cell (not_cell) {
bus (A) {
bus_type : "bus8" ;
direction : "input" ;
}
pin (Y) {
function : !A[0] ;
direction : "output" ;
original_pin : A[0] ;
}
}
}

8
tests/liberty/busdef2.lib.filtered.ok
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library(liberty_define) {
cell(not_cell) {
pin(Y) {
function : !A[0] ;
direction : output ;
}
}
}

4
tests/liberty/busdef2.lib.verilogsim.ok
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module not_cell (Y);
output Y;
assign Y = !A[0]; // !A[0]
endmodule

1
tests/peepopt/.gitignore vendored
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/*.log