Merge branch 'YosysHQ:main' into main

Makefile

@@ -170,7 +170,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.50+1
+YOSYS_VER := 0.50+7
 
 # Note: We arrange for .gitcommit to contain the (short) commit hash in
 # tarballs generated with git-archive(1) using .gitattributes. The git repo

passes/opt/opt_expr.cc

@@ -1333,6 +1333,10 @@ skip_fine_alu:
 			RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
 			RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
 
+			// Limit indexing to the size of a, which is behaviourally identical (result is all 0)
+			// and avoids integer overflow of i + shift_bits when e.g. ID::B == INT_MAX
+			shift_bits = min(shift_bits, GetSize(sig_a));
+
 			if (cell->type != ID($shiftx) && GetSize(sig_a) < GetSize(sig_y))
 				sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
 

tests/opt/opt_expr_shr_int_max.ys

@@ -0,0 +1,9 @@
+read_verilog << EOF
+module uut_00034(b, y);
+  input signed [30:0] b;
+  output [11:0] y = b >> ~31'b0; // shift by INT_MAX
+endmodule
+EOF
+
+# This should succeed, even with UBSAN halt_on_error
+opt_expr