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abstract: test -init

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Emil J. Tywoniak 2025-02-19 23:03:43 +01:00
parent 925c617c52
commit 5bd18613bb
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tests/various/abstract_init.ys Normal file
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design -reset
read_verilog <<EOT
module foo (CLK, Q, QQQ);
input CLK;
output reg QQQ;
output reg Q = 1'b1;
assign QQQ = Q;
always @(posedge CLK)
Q <= ~Q;
endmodule
EOT
proc
opt_expr
opt_dff
select -assert-count 1 w:Q a:init %i
abstract -init w:QQQ
check -assert
select -assert-count 0 w:Q a:init %i
design -reset
read_verilog <<EOT
module foo (CLK, Q, QQQ);
input CLK;
output reg QQQ;
output reg [1:0] Q = 1'b1;
assign QQQ = Q;
always @(posedge CLK)
Q <= ~Q;
endmodule
EOT
proc
opt_expr
opt_dff
select -assert-count 1 w:Q a:init=2'b01 %i
abstract -init w:QQQ
check -assert
select -assert-count 1 w:Q a:init=2'b0x %i