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opt_clean, simplemap: Add $buf handling

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This commit is contained in:
Martin Povišer 2025-03-07 12:07:02 +01:00
parent 55595b6c8d
commit 557047fe1e
4 changed files with 24 additions and 2 deletions
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13
tests/techmap/buf.ys Normal file
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read_verilog -icells <<EOF
module top(input wire [2:0] a, output wire [2:0] y);
\$buf #(.WIDTH(3)) b(.A(a), .Y(y));
endmodule
EOF
design -save save
opt_clean
select -assert-none t:$buf
design -load save
techmap
select -assert-none t:$buf