mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-23 00:55:32 +00:00
Code Activity

stat: allow gzipped liberty files

Browse source
This commit is contained in:
Emil J. Tywoniak 2025-01-27 16:08:47 +01:00
parent 7aefd4b226
commit 980a0a15c1
2 changed files with 19 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

14
tests/various/stat.ys Normal file
View file

@ -0,0 +1,14 @@
read_rtlil << EOF
module \top
wire input 1 \A
wire output 2 \Y
cell \sg13g2_and2_1 \sub
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
EOF
logger -expect log "Chip area for module '\\top': 9.072000" 1
logger -expect-no-warnings
stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz