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Merge remote-tracking branch 'upstream/main'

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Akash Levy 2025-03-12 19:21:32 -07:00
commit e4066b784d
23 changed files with 425 additions and 60 deletions
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61
tests/alumacc/basic.ys Normal file
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read_verilog <<EOF
module gate(input signed [2:0] a1, input signed [2:0] b1,
input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
wire signed [3:0] ab1;
assign ab1 = a1 * b1;
assign y = ab1 + a2*b2 + c + d + 1;
endmodule
EOF
prep
equiv_opt -assert alumacc
design -load postopt
stat
design -save save
equiv_opt -assert maccmap
design -load save
equiv_opt -assert maccmap -unmap
design -reset
read_verilog <<EOF
module gate(input signed [2:0] a1, input signed [1:0] b1, output signed [3:0] y);
assign y = a1 * b1;
endmodule
EOF
prep
equiv_opt -assert alumacc
design -load postopt
stat
design -save save
equiv_opt -assert maccmap
design -load save
equiv_opt -assert maccmap -unmap
design -reset
read_verilog <<EOF
module gate(input [2:0] a, input [1:0] b, output [3:0] y);
assign y = a * b;
endmodule
EOF
prep
equiv_opt -assert alumacc
design -load postopt
stat
design -save save
equiv_opt -assert maccmap
design -load save
equiv_opt -assert maccmap -unmap
design -reset
read_verilog <<EOF
module gate(input [2:0] a, input [1:0] b, input [1:0] c, output [3:0] y);
assign y = a * b - c;
endmodule
EOF
prep
equiv_opt -assert alumacc
design -load postopt
stat
design -save save
equiv_opt -assert maccmap
design -load save
equiv_opt -assert maccmap -unmap

19
tests/alumacc/macc_infer_n_unmap.ys Normal file
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read_verilog <<EOF
module gate(input signed [2:0] a1, input signed [2:0] b1,
input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
wire signed [3:0] ab1;
assign ab1 = a1 * b1;
assign y = ab1 + a2*b2 + c + d + 1;
endmodule
EOF
prep
design -save gold
alumacc
opt_clean
select -assert-count 1 t:$macc_v2
maccmap -unmap
design -copy-from gold -as gold gate
equiv_make gold gate equiv
equiv_induct equiv
equiv_status -assert equiv