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Merge branch 'YosysHQ:main' into main

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Akash Levy 2025-03-10 14:21:49 -07:00 • committed by GitHub
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tests/techmap/buf.ys Normal file
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read_verilog -icells <<EOF
module top(input wire [2:0] a, output wire [2:0] y);
\$buf #(.WIDTH(3)) b(.A(a), .Y(y));
endmodule
EOF
design -save save
opt_clean
select -assert-none t:$buf
design -load save
techmap
select -assert-none t:$buf