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Merge nice gzip refactor

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This commit is contained in:
Akash Levy 2025-03-20 16:47:12 -07:00
commit 95f489beec
23 changed files with 719 additions and 575 deletions
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14
tests/various/stat.ys Normal file
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read_rtlil << EOF
module \top
wire input 1 \A
wire output 2 \Y
cell \sg13g2_and2_1 \sub
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
EOF
logger -expect log "Chip area for module '\\top': 9.072000" 1
logger -expect-no-warnings
stat -liberty ../../tests/liberty/foundry_data/sg13g2_stdcell_typ_1p20V_25C.lib.filtered.gz