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opt_merge: fix trivial binary regression

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This commit is contained in:
Emil J. Tywoniak 2025-03-10 11:43:13 +01:00
parent 8903740147
commit 176faae7c9
2 changed files with 13 additions and 1 deletions
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1
passes/opt/opt_merge.cc
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@ -95,7 +95,6 @@ struct OptMergeWorker
};
std::sort(inputs.begin(), inputs.end());
h = hash_ops<std::array<RTLIL::SigSpec, 2>>::hash_into(inputs, h);
h = assign_map(cell->getPort(ID::Y)).hash_into(h);
} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
SigSpec a = assign_map(cell->getPort(ID::A));
a.sort();

13
tests/opt/opt_merge_basic.ys Normal file
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@ -0,0 +1,13 @@
read_verilog -icells <<EOT
module top(A, B, X, Y);
input [8:0] A, B;
output [8:0] X, Y;
assign X = A + B;
assign Y = A + B;
endmodule
EOT
select -assert-count 2 t:$add
equiv_opt -assert opt_merge
design -load postopt
select -assert-count 1 t:$add