mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
Merge branch 'YosysHQ:main' into main
This commit is contained in:
Akash Levy
GitHub
commit
9d3b7f7474
13 changed files with 1019 additions and 10 deletions
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|
@ -5,7 +5,22 @@ YOSYS_NAMESPACE_BEGIN
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|||
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namespace RTLIL {
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class KernelRtlilTest : public testing::Test {};
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struct SafePrintToStringParamName {
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template <class ParamType>
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std::string operator()(const testing::TestParamInfo<ParamType>& info) const {
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std::string name = testing::PrintToString(info.param);
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for (auto &c : name)
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if (!('0' <= c && c <= '9') && !('a' <= c && c <= 'z') && !('A' <= c && c <= 'Z') ) c = '_';
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return name;
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}
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};
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class KernelRtlilTest : public testing::Test {
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protected:
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KernelRtlilTest() {
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if (log_files.empty()) log_files.emplace_back(stdout);
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}
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};
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TEST_F(KernelRtlilTest, ConstAssignCompare)
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{
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@ -74,6 +89,83 @@ namespace RTLIL {
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}
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}
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class WireRtlVsHdlIndexConversionTest :
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public KernelRtlilTest,
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public testing::WithParamInterface<std::tuple<bool, int, int>>
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{};
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INSTANTIATE_TEST_SUITE_P(
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WireRtlVsHdlIndexConversionInstance,
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WireRtlVsHdlIndexConversionTest,
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testing::Values(
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std::make_tuple(false, 0, 10),
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std::make_tuple(true, 0, 10),
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std::make_tuple(false, 4, 10),
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std::make_tuple(true, 4, 10),
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std::make_tuple(false, -4, 10),
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std::make_tuple(true, -4, 10),
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std::make_tuple(false, 0, 1),
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std::make_tuple(true, 0, 1),
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std::make_tuple(false, 4, 1),
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std::make_tuple(true, 4, 1),
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std::make_tuple(false, -4, 1),
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std::make_tuple(true, -4, 1)
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),
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SafePrintToStringParamName()
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);
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TEST_P(WireRtlVsHdlIndexConversionTest, WireRtlVsHdlIndexConversion) {
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std::unique_ptr<Module> mod = std::make_unique<Module>();
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Wire *wire = mod->addWire(ID(test), 10);
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auto [upto, start_offset, width] = GetParam();
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wire->upto = upto;
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wire->start_offset = start_offset;
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wire->width = width;
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int smallest = INT_MAX;
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int largest = INT_MIN;
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for (int i = 0; i < wire->width; i++) {
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int j = wire->to_hdl_index(i);
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smallest = std::min(smallest, j);
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largest = std::max(largest, j);
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EXPECT_EQ(
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std::make_pair(wire->from_hdl_index(j), j),
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std::make_pair(i, wire->to_hdl_index(i))
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);
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}
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EXPECT_EQ(smallest, start_offset);
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EXPECT_EQ(largest, start_offset + wire->width - 1);
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for (int i = 1; i < wire->width; i++) {
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EXPECT_EQ(
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wire->to_hdl_index(i) - wire->to_hdl_index(i - 1),
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upto ? -1 : 1
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);
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}
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for (int j = smallest; j < largest; j++) {
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int i = wire->from_hdl_index(j);
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EXPECT_EQ(
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std::make_pair(wire->from_hdl_index(j), j),
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std::make_pair(i, wire->to_hdl_index(i))
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);
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}
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for (int i = -10; i < 0; i++)
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EXPECT_EQ(wire->to_hdl_index(i), INT_MIN);
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for (int i = wire->width; i < wire->width + 10; i++)
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EXPECT_EQ(wire->to_hdl_index(i), INT_MIN);
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for (int j = smallest - 10; j < smallest; j++)
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EXPECT_EQ(wire->from_hdl_index(j), INT_MIN);
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for (int j = largest + 1; j < largest + 11; j++)
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EXPECT_EQ(wire->from_hdl_index(j), INT_MIN);
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}
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}
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YOSYS_NAMESPACE_END
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|
|
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121
tests/various/abstract_init.ys
Normal file
121
tests/various/abstract_init.ys
Normal file
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@ -0,0 +1,121 @@
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q, QQQ);
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input CLK;
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output reg QQQ;
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output reg Q = 1'b1;
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assign QQQ = Q;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init %i
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abstract -init w:QQQ
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check -assert
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select -assert-count 0 w:Q a:init %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q, QQQ);
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input CLK;
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output reg QQQ;
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output reg [1:0] Q = 1'b1;
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assign QQQ = Q;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init w:QQQ
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// downto
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output reg [1:0] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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design -save basic
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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design -load basic
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0:1 w:Q
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check -assert
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select -assert-count 0 w:Q a:init %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// downto
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output reg [1:0] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -rtlilslice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// upto
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output reg [0:1] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'bx1 %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// upto
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output reg [0:1] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -rtlilslice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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178
tests/various/abstract_state.ys
Normal file
178
tests/various/abstract_state.ys
Normal file
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@ -0,0 +1,178 @@
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read_verilog <<EOT
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module half_clock (CLK, Q, magic);
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input CLK;
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output reg Q;
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input magic;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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design -save half_clock
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# -----------------------------------------------------------------------------
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# An empty selection causes no change
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select -none
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logger -expect log "Abstracted 0 stateful cells" 1
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abstract -state -enablen magic
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logger -check-expected
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logger -expect log "Abstracted 0 init bits" 1
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abstract -init
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logger -check-expected
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logger -expect log "Abstracted 0 driver ports" 1
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abstract -value -enablen magic
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logger -check-expected
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select -clear
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# -----------------------------------------------------------------------------
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design -load half_clock
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# Basic -state test
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abstract -state -enablen magic
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check -assert
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# Connections to dff D input port
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select -set conn_to_d t:$dff %x:+[D] t:$dff %d
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# The D input port is fed with a mux
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select -set mux @conn_to_d %ci t:$mux %i
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select -assert-count 1 @mux
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# The S input port is fed with the magic wire
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select -assert-count 1 @mux %x:+[S] w:magic %i
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# The A input port is fed with an anyseq
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select -assert-count 1 @mux %x:+[A] %ci t:$anyseq %i
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# The B input port is fed with the negated Q
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select -set not @mux %x:+[B] %ci t:$not %i
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select -assert-count 1 @not %x:+[A] o:Q %i
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design -load half_clock
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# Same thing, inverted polarity
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abstract -state -enable magic
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check -assert
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select -set conn_to_d t:$dff %x:+[D] t:$dff %d
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select -set mux @conn_to_d %ci t:$mux %i
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select -assert-count 1 @mux
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select -assert-count 1 @mux %x:+[S] w:magic %i
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# so we get swapped A and B
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select -assert-count 1 @mux %x:+[B] %ci t:$anyseq %i
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select -set not @mux %x:+[A] %ci t:$not %i
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select -assert-count 1 @not %x:+[A] o:Q %i
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# -----------------------------------------------------------------------------
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design -reset
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read_verilog <<EOT
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module wide_flop_no_q (CLK, DDD, QQQ, magic);
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input CLK;
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input [2:0] DDD;
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output reg [2:0] QQQ;
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input magic;
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always @(posedge CLK)
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QQQ <= DDD;
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endmodule
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||||
EOT
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proc
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opt_expr
|
||||
opt_dff
|
||||
dump
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||||
abstract -state -enablen magic -slice 0 w:QQQ
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||||
check -assert
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||||
# Connections to dff D input port
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select -set conn_to_d t:$dff %x:+[D] t:$dff %d
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# The D input port is partially fed with a mux
|
||||
select -set mux @conn_to_d %ci t:$mux %i
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select -assert-count 1 @mux
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# and also the DDD input
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select -assert-count 1 @conn_to_d w:DDD %i
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||||
# The S input port is fed with the magic wire
|
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select -assert-count 1 @mux %x:+[S] w:magic %i
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# The A input port is fed with an anyseq
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select -assert-count 1 @mux %x:+[A] %ci t:$anyseq %i
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# The B input port is fed with DDD
|
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select -assert-count 1 @mux %x:+[B] %ci w:DDD %i
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||||
# -----------------------------------------------------------------------------
|
||||
# Selecting wire Q connected to bit 0 of QQQ is the same as specifying
|
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# QQQ with the -slice 0 argument
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design -reset
|
||||
read_verilog <<EOT
|
||||
module wide_flop (CLK, DDD, QQQ, Q, magic);
|
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input CLK;
|
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input [2:0] DDD;
|
||||
output reg [2:0] QQQ;
|
||||
output reg Q;
|
||||
input magic;
|
||||
always @(posedge CLK)
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QQQ <= DDD;
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||||
assign Q = QQQ[0];
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
design -save wide_flop
|
||||
# Test that abstracting an output slice muxes an input slice
|
||||
abstract -state -enablen magic w:Q
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||||
check -assert
|
||||
# Same testing as previous case
|
||||
select -set conn_to_d t:$dff %x:+[D] t:$dff %d
|
||||
select -set mux @conn_to_d %ci t:$mux %i
|
||||
select -assert-count 1 @mux
|
||||
select -assert-count 1 @conn_to_d w:DDD %i
|
||||
select -assert-count 1 @mux %x:+[S] w:magic %i
|
||||
select -assert-count 1 @mux %x:+[A] %ci t:$anyseq %i
|
||||
select -assert-count 1 @mux %x:+[B] %ci w:DDD %i
|
||||
# -----------------------------------------------------------------------------
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module half_clock_en (CLK, E, Q, magic);
|
||||
input CLK;
|
||||
input E;
|
||||
output reg Q;
|
||||
input magic;
|
||||
always @(posedge CLK)
|
||||
if (E)
|
||||
Q <= ~Q;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
opt_expr
|
||||
opt_dff
|
||||
design -save half_clock_en
|
||||
# Test that abstracting a $dffe unmaps the enable
|
||||
select -assert-count 1 t:$dffe
|
||||
abstract -state -enablen magic
|
||||
check -assert
|
||||
select -assert-count 0 t:$dffe
|
||||
select -assert-count 1 t:$dff
|
||||
# -----------------------------------------------------------------------------
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module top (CLK, E, Q, Q_EN);
|
||||
input CLK;
|
||||
input E;
|
||||
output reg Q;
|
||||
output reg Q_EN;
|
||||
half_clock uut (CLK, Q, 1'b0);
|
||||
half_clock_en uut_en (CLK, E, Q_EN, 1'b0);
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
design -import half_clock
|
||||
design -import half_clock_en
|
||||
hierarchy -check -top top
|
||||
# Test when the abstraction is disabled (enable is inactive),
|
||||
# the equivalence is preserved
|
||||
rename top top_gold
|
||||
design -save gold
|
||||
abstract -state -enable magic half_clock half_clock_en
|
||||
flatten
|
||||
rename top_gold top_gate
|
||||
design -save gate
|
||||
design -load gold
|
||||
flatten
|
||||
design -import gate -as top_gate
|
||||
|
||||
equiv_make top_gold top_gate equiv
|
||||
equiv_induct equiv
|
||||
equiv_status -assert equiv
|
||||
# The reader may verify that this model checking is functional
|
||||
# by changing -enable to -enablen in the abstract pass invocation above
|
||||
# -----------------------------------------------------------------------------
|
||||
95
tests/various/abstract_value.ys
Normal file
95
tests/various/abstract_value.ys
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
read_verilog <<EOT
|
||||
module split_output (A, B, Y, magic);
|
||||
input [1:0] A;
|
||||
input [1:0] B;
|
||||
output [1:0] Y;
|
||||
input magic;
|
||||
wire W;
|
||||
assign Y = A + B;
|
||||
assign W = Y[0]; // <--- look here
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
design -save split_output
|
||||
# Basic -value test
|
||||
abstract -value -enable magic w:W
|
||||
check -assert
|
||||
# Connections to $add Y output port
|
||||
select -set conn_to_y t:$add %x:+[Y] t:$add %d
|
||||
# The $add Y output port feeds partially into a mux
|
||||
select -set mux @conn_to_y %ci t:$mux %i
|
||||
select -assert-count 1 @mux
|
||||
# and also the Y module output
|
||||
select -assert-count 1 @conn_to_y %a o:Y %i
|
||||
# The S input port is fed with the magic wire
|
||||
select -assert-count 1 @mux %x:+[S] w:magic %i
|
||||
# The B input port is fed with an anyseq
|
||||
select -assert-count 1 @mux %x:+[B] %ci t:$anyseq %i
|
||||
# The Y output port feeds into the Y module output
|
||||
select -assert-count 1 @mux %x:+[Y] %co o:Y %i
|
||||
# -----------------------------------------------------------------------------
|
||||
# Same thing, but we use -slice instead of wire W
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module split_output_no_w (A, B, Y, magic);
|
||||
input [1:0] A;
|
||||
input [1:0] B;
|
||||
output [1:0] Y;
|
||||
input magic;
|
||||
assign Y = A + B;
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
# Same test as the previous case
|
||||
abstract -value -enable magic -slice 0 w:Y
|
||||
check -assert
|
||||
select -set conn_to_y t:$add %x:+[Y] t:$add %d
|
||||
select -set mux @conn_to_y %ci t:$mux %i
|
||||
select -assert-count 1 @mux
|
||||
select -assert-count 1 @conn_to_y %a o:Y %i
|
||||
select -assert-count 1 @mux %x:+[S] w:magic %i
|
||||
select -assert-count 1 @mux %x:+[B] %ci t:$anyseq %i
|
||||
select -assert-count 1 @mux %x:+[Y] %co o:Y %i
|
||||
# -----------------------------------------------------------------------------
|
||||
design -reset
|
||||
read_verilog <<EOT
|
||||
module split_input (A, B, Y, magic);
|
||||
input [1:0] A;
|
||||
input [1:0] B;
|
||||
output [1:0] Y;
|
||||
input magic;
|
||||
wire W;
|
||||
assign Y = A + B;
|
||||
assign W = A[0]; // <--- look here
|
||||
endmodule
|
||||
EOT
|
||||
proc
|
||||
design -save split_input
|
||||
# The mux goes on an input this time
|
||||
abstract -value -enable magic w:W
|
||||
check -assert
|
||||
# Connections to add A input port
|
||||
select -set conn_to_a t:$add %x:+[A] t:$add %d
|
||||
# The B input port is partially fed with a mux
|
||||
select -set mux @conn_to_a %ci t:$mux %i
|
||||
select -assert-count 1 @mux
|
||||
# and also the A input
|
||||
select -assert-count 1 @conn_to_a %a w:A %i
|
||||
# The S input port is fed with the magic wire
|
||||
select -assert-count 1 @mux %x:+[S] w:magic %i
|
||||
# The A input port is fed with the module input A
|
||||
select -assert-count 1 @mux %x:+[A] %ci i:A %i
|
||||
# The B input port is fed with an anyseq
|
||||
select -assert-count 1 @mux %x:+[B] %ci t:$anyseq %i
|
||||
# -----------------------------------------------------------------------------
|
||||
# All wires selected, excluding magic -> muxes on inputs and outputs
|
||||
design -load split_output
|
||||
select -assert-count 0 t:$mux
|
||||
abstract -value -enable magic w:* w:magic %d
|
||||
select -assert-count 3 t:$mux
|
||||
# All cells selected -> muxes on outputs only
|
||||
design -load split_output
|
||||
select -assert-count 0 t:$mux
|
||||
abstract -value -enable magic t:*
|
||||
select -assert-count 1 t:$mux
|
||||
# -----------------------------------------------------------------------------
|
||||
Loading…
Add table
Add a link
Reference in a new issue