Cleanup

Brewfile

@@ -12,6 +12,7 @@ brew "bash"
 brew "boost-python3"
 brew "llvm"
 brew "lld"
+brew "m4"
 brew "autoconf"
 
 brew "dwarfutils"

Makefile

@@ -123,7 +123,6 @@ BISON ?= bison
 STRIP ?= strip
 AWK ?= awk
 
-
 ifeq ($(OS), Linux)
 LIBS += -ldw                  # SILIMATE: support for backward-cpp
 CXXFLAGS += -I/usr/include/libdwarf/ -DBACKWARD_HAS_DW # SILIMATE: support for backward-cpp
@@ -711,32 +710,19 @@ include $(YOSYS_SRC)/frontends/blif/Makefile.inc
 include $(YOSYS_SRC)/frontends/liberty/Makefile.inc
 include $(YOSYS_SRC)/passes/equiv/Makefile.inc
 
-OBJS += passes/cmds/select.o
-OBJS += passes/cmds/show.o
-OBJS += passes/cmds/stat.o
-OBJS += passes/cmds/cover.o
-OBJS += passes/cmds/design.o
-OBJS += passes/cmds/plugin.o
-OBJS += passes/cmds/annotate_logic_depth.o
-OBJS += passes/cmds/blackbox.o
-OBJS += passes/cmds/check.o
-OBJS += passes/cmds/clean_zerowidth.o
-OBJS += passes/cmds/selectconst.o
-OBJS += passes/cmds/setattr.o
-OBJS += passes/cmds/splitcells.o
-OBJS += passes/cmds/annotate_cell_fanout.o
-OBJS += passes/cmds/splitfanout.o
-OBJS += passes/cmds/splitnets.o
-OBJS += passes/cmds/tee.o
-OBJS += passes/cmds/activity.o
-OBJS += passes/cmds/splitnetlist.o
-OBJS += passes/cmds/bus_rebuild.o
-OBJS += passes/cmds/longloop_select.o
+include $(YOSYS_SRC)/passes/cmds/Makefile.inc
+include $(YOSYS_SRC)/passes/silimate/Makefile.inc
+
+OBJS += passes/opt/pmux2shiftx.o
+OBJS += passes/opt/muxpack.o
 OBJS += passes/sat/sim.o
-OBJS += passes/techmap/bufnorm.o
-OBJS += passes/cmds/rename.o
-OBJS += passes/cmds/segv.o
-OBJS += passes/cmds/delete.o
+OBJS += passes/techmap/extract.o
+OBJS += passes/techmap/extract_reduce.o
+OBJS += passes/techmap/alumacc.o
+OBJS += passes/techmap/pmuxtree.o
+OBJS += passes/techmap/bmuxmap.o
+OBJS += passes/techmap/demuxmap.o
+OBJS += passes/techmap/aigmap.o
 
 include $(YOSYS_SRC)/passes/hierarchy/Makefile.inc
 include $(YOSYS_SRC)/passes/memory/Makefile.inc

frontends/verific/verific.cc

@@ -4564,10 +4564,8 @@ struct ReadPass : public Pass {
 				args[0] = "verific";
 			} else {
 				args[0] = "read_verilog";
-				if (args[1] == "-formal") {
+				if (args[1] == "-formal")
 					args.insert(args.begin()+1, std::string());
-					RuntimeFlags::SetVar("veri_ignore_assertion_statements", 0);
-				}
 				args[1] = "-sv";
 				args.insert(args.begin()+1, "-defer");
 			}

passes/cmds/Makefile.inc

@@ -6,7 +6,6 @@ OBJS += passes/cmds/add.o
 OBJS += passes/cmds/delete.o
 OBJS += passes/cmds/design.o
 OBJS += passes/cmds/select.o
-OBJS += passes/cmds/selectconst.o
 OBJS += passes/cmds/show.o
 OBJS += passes/cmds/viz.o
 OBJS += passes/cmds/rename.o
@@ -16,7 +15,6 @@ OBJS += passes/cmds/scatter.o
 OBJS += passes/cmds/setundef.o
 OBJS += passes/cmds/splitnets.o
 OBJS += passes/cmds/splitcells.o
-OBJS += passes/cmds/splitfanout.o
 OBJS += passes/cmds/stat.o
 OBJS += passes/cmds/internal_stats.o
 OBJS += passes/cmds/setattr.o
@@ -53,10 +51,5 @@ OBJS += passes/cmds/future.o
 OBJS += passes/cmds/box_derive.o
 OBJS += passes/cmds/example_dt.o
 OBJS += passes/cmds/portarcs.o
-
-OBJS += passes/cmds/activity.o
-OBJS += passes/cmds/splitnetlist.o
-OBJS += passes/cmds/bus_rebuild.o
-
 OBJS += passes/cmds/wrapcell.o
 OBJS += passes/cmds/setenv.o

passes/opt/Makefile.inc

@@ -12,16 +12,14 @@ OBJS += passes/opt/opt_share.o
 OBJS += passes/opt/opt_clean.o
 OBJS += passes/opt/opt_expr.o
 
-OBJS += passes/opt/opt_balance_tree.o
-OBJS += passes/opt/muxpack.o
-OBJS += passes/opt/wreduce.o
-OBJS += passes/opt/pmux2shiftx.o
-
 ifneq ($(SMALL),1)
 OBJS += passes/opt/share.o
+OBJS += passes/opt/wreduce.o
 OBJS += passes/opt/opt_demorgan.o
 OBJS += passes/opt/rmports.o
 OBJS += passes/opt/opt_lut.o
 OBJS += passes/opt/opt_lut_ins.o
 OBJS += passes/opt/opt_ffinv.o
+OBJS += passes/opt/pmux2shiftx.o
+OBJS += passes/opt/muxpack.o
 endif

passes/silimate/Makefile.inc

@@ -0,0 +1,11 @@
+
+OBJS += passes/silimate/activity.o
+OBJS += passes/silimate/annotate_cell_fanout.o
+OBJS += passes/silimate/annotate_logic_depth.o
+OBJS += passes/silimate/breaksop.o
+OBJS += passes/silimate/bus_rebuild.o
+OBJS += passes/silimate/longloop_select.o
+OBJS += passes/silimate/opt_balance_tree.o
+OBJS += passes/silimate/selectconst.o
+OBJS += passes/silimate/splitfanout.o
+OBJS += passes/silimate/splitnetlist.o

passes/techmap/Makefile.inc

@@ -7,15 +7,6 @@ OBJS += passes/techmap/maccmap.o
 OBJS += passes/techmap/booth.o
 OBJS += passes/techmap/libparse.o
 
-OBJS += passes/techmap/bmuxmap.o
-OBJS += passes/techmap/demuxmap.o
-OBJS += passes/techmap/pmuxtree.o
-OBJS += passes/techmap/alumacc.o
-OBJS += passes/techmap/extract.o
-OBJS += passes/techmap/extract_reduce.o
-OBJS += passes/techmap/aigmap.o
-OBJS += passes/techmap/breaksop.o
-
 ifeq ($(ENABLE_ABC),1)
 OBJS += passes/techmap/abc.o
 OBJS += passes/techmap/abc9.o
@@ -34,11 +25,18 @@ ifneq ($(SMALL),1)
 OBJS += passes/techmap/iopadmap.o
 OBJS += passes/techmap/clkbufmap.o
 OBJS += passes/techmap/hilomap.o
+OBJS += passes/techmap/extract.o
 OBJS += passes/techmap/extract_fa.o
 OBJS += passes/techmap/extract_counter.o
+OBJS += passes/techmap/extract_reduce.o
+OBJS += passes/techmap/alumacc.o
 OBJS += passes/techmap/dffinit.o
+OBJS += passes/techmap/pmuxtree.o
+OBJS += passes/techmap/bmuxmap.o
+OBJS += passes/techmap/demuxmap.o
 OBJS += passes/techmap/bwmuxmap.o
 OBJS += passes/techmap/muxcover.o
+OBJS += passes/techmap/aigmap.o
 OBJS += passes/techmap/tribuf.o
 OBJS += passes/techmap/lut2mux.o
 OBJS += passes/techmap/nlutmap.o

passes/techmap/bufnorm.cc

@@ -391,7 +391,7 @@ struct BufnormPass : public Pass {
 					}
 
 					if (w->name.isPublic())
-						log_debug("  directly driven by cell %s port %s: %s\n",
+						log("  directly driven by cell %s port %s: %s\n",
 								log_id(cell), log_id(conn.first), log_id(w));
 
 					for (auto bit : SigSpec(w))

passes/techmap/libparse.cc

@@ -389,12 +389,9 @@ LibertyAst *LibertyParser::parse()
 			if (tok == 'v') {
     				tok = lexer(str);
 			}
-			while (tok == '(' || tok == ')' || tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') { // SILIMATE: added parentheses
+			while (tok == '+' || tok == '-' || tok == '*' || tok == '/' || tok == '!') {
 				ast->value += tok;
-				if (tok == ')') { // SILIMATE: semicolon may follow close parenthesis
-					tok = lexer(str);
-					if (tok == ';') break;
-				} else tok = lexer(str);
+				tok = lexer(str);
 				if (tok != 'v')
 					error();
 				ast->value += str;
@@ -407,13 +404,6 @@ LibertyAst *LibertyParser::parse()
 			// instead of the ';' too..
 			if ((tok == ';') || (tok == 'n'))
 				break;
-			else if (tok == '[') {
-				while (tok != ']') {
-					tok = lexer(str);
-				}
-				ast->value += '[' + str + ']';
-				continue;
-			}
 			else
 				error();
 			continue;
@@ -475,16 +465,12 @@ LibertyAst *LibertyParser::parse()
 					{
 					case 'n':
 					  continue;
-					case ':': // SILIMATE HACK: eat up the ':' and the next thing too
-						tok = lexer(arg);
-						if (tok != 'v')
-							error("Expecting string after ':'.");
-						break;
 					case '[':
 					case ']':
 					case '}':
 					case '{':
 					case '\"':
+					case ':':
 						eReport = "Unexpected '";
 						eReport += static_cast<char>(tok);
 						eReport += "'.";

tests/liberty/busdef2.lib

@@ -1,45 +0,0 @@
-/* Tests two things:                                                      */
-/* (1) Bus without any individual pin definition                          */
-/* (2) Having a custom field with define, which can allow square brackets */
-library (liberty_define) {
-  delay_model : "table_lookup" ;
-  simulation : false ;
-  capacitive_load_unit (1,pF) ;
-  leakage_power_unit : "1pW" ;
-  current_unit : "1A" ;
-  pulling_resistance_unit : "1kohm" ;
-  time_unit : "1ns" ;
-  voltage_unit : "1v" ;
-  library_features : "report_delay_calculation" ;
-  input_threshold_pct_rise : 50 ;
-  input_threshold_pct_fall : 50 ;
-  output_threshold_pct_rise : 50 ;
-  output_threshold_pct_fall : 50 ;
-  slew_lower_threshold_pct_rise : 30 ;
-  slew_lower_threshold_pct_fall : 30 ;
-  slew_upper_threshold_pct_rise : 70 ;
-  slew_upper_threshold_pct_fall : 70 ;
-  slew_derate_from_library : 1.0 ;
-  nom_process : 1.0 ;
-  nom_temperature : 85.0 ;
-  nom_voltage : 0.75 ;
-  type (bus8) {
-    base_type : "array";
-    data_type : "bit";
-    bit_width : 8;
-    bit_from : 7;
-    bit_to : 0;
-  }
-  define (original_pin, pin, string) ;
-  cell (not_cell) {
-    bus (A) {
-      bus_type : "bus8" ;
-      direction : "input" ;
-    }
-    pin (Y) {
-      function : !A[0] ;
-      direction : "output" ;
-      original_pin : A[0] ;
-    }
-  }
-}

tests/liberty/busdef2.lib.filtered.ok

@@ -1,8 +0,0 @@
-library(liberty_define) {
-  cell(not_cell) {
-    pin(Y) {
-      function : !A[0] ;
-      direction : output ;
-    }
-  }
-}

tests/liberty/busdef2.lib.verilogsim.ok

@@ -1,4 +0,0 @@
-module not_cell (Y);
-  output Y;
-  assign Y = !A[0]; // !A[0]
-endmodule

tests/peepopt/.gitignore

@@ -1 +0,0 @@
-/*.log