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Code Activity
10808 commits 94 branches 53 tags 44 MiB
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1430 commits

Author SHA1 Message Date
Diego H
937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Eddie Hung
23fcfd0adb Make SV2017 compliant courtesy of @wsnyder 2019-12-12 07:34:07 -08:00
Eddie Hung
4a80510877 Even more obvious testcase 2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b Make testcase clearer with \o having its own init 2019-12-11 23:48:09 -08:00
Eddie Hung
151f7533e8 Add testcase 2019-12-11 16:52:37 -08:00
Eddie Hung
e75ca29b19 Add test: 'Warning: ignoring initial value on non-register: \o' 2019-12-11 11:26:54 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33 unmap $__ICE40_CARRY_WRAPPER in test 2019-12-09 14:20:35 -08:00
Eddie Hung
705e520a52 Add a quick testcase for unknown modules as inout 2019-12-09 13:14:46 -08:00
Eddie Hung
e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
Miodrag Milanovic
49c9b63e0f Fix for non-deterministic test 2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980 Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:02 -08:00
Eddie Hung
19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Eddie Hung
67f1ce2d43 Check SB_CARRY name also preserved 2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4 Add testcase 2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5 update test 2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
David Shah
e9ce4e658b abc9: Fix breaking of SCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 20:44:56 +00:00
Eddie Hung
c61186dd9d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-27 13:24:03 -08:00
Eddie Hung
ff1e357682 Add multiple driver testcase 2019-11-27 13:22:26 -08:00
Eddie Hung
4bac6b13be Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-27 10:17:10 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd 
xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
 2019-11-27 08:00:22 -08:00
Clifford Wolf
f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix 
opt_share: Fix handling of fine cells.
 2019-11-27 11:23:16 +01:00
Eddie Hung
f6c0ec1d09 Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff 2019-11-27 01:03:33 -08:00
Eddie Hung
6338615aa1 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-27 01:02:16 -08:00
Eddie Hung
8c813632b6 Revert "submod to bitty rather bussy, for bussy wires used as input and output" 
This reverts commit cba3073026.
 2019-11-27 00:48:22 -08:00
Eddie Hung
6318e3ce6d Fix wire width 2019-11-26 23:38:49 -08:00
Eddie Hung
de3476cc23 No need for -abc9 2019-11-26 23:08:14 -08:00
Marcin Kościelnicki
fdcbda195b opt_share: Fix handling of fine cells. 
Fixes #1525.
 2019-11-27 08:01:07 +01:00
Eddie Hung
4a0198128e Add citation 2019-11-26 22:51:16 -08:00
Eddie Hung
15042eaf57 Remove notes 2019-11-26 22:41:35 -08:00
Eddie Hung
222e199b73 Add testcase derived from fastfir_dynamictaps benchmark 2019-11-26 21:26:30 -08:00
Eddie Hung
dd317c9280 Add testcase where \init is copied 2019-11-25 16:07:35 -08:00
Eddie Hung
d087024caf Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-25 12:42:09 -08:00
Marcin Kościelnicki
6cdea425b8 clkbufmap: Add support for inverters in clock path. 2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e xilinx: Use INV instead of LUT1 when applicable 2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910 attempt to fix formatting 2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a gowin: add and test dff init values 2019-11-25 14:33:21 +01:00
Eddie Hung
b46e636c91 Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff 2019-11-23 08:38:48 -08:00
Eddie Hung
d223e11a72 Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 22:28:35 -08:00
Eddie Hung
5cd3d3db0a Remove redundant flatten 2019-11-22 22:28:10 -08:00
Eddie Hung
08f85e6438 Stray dump 2019-11-22 20:53:48 -08:00
Eddie Hung
2c5dfd802d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-22 17:24:45 -08:00
Eddie Hung
4fdcf8f7d7 Add another test with constant driver 2019-11-22 17:23:34 -08:00
Eddie Hung
74ea438136 Add testcase for signal used as part input part output 2019-11-22 16:52:55 -08:00