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Add a quick testcase for unknown modules as inout
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@ -80,9 +80,8 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog -icells <<EOT
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read_verilog <<EOT
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module top(input d, c, (* init = 3'b011 *) output reg [2:0] q);
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(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
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DFF s2(.D(d), .C(c), .Q(q[0]));
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@ -100,3 +99,26 @@ proc
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submod
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dffinit -ff DFF Q INIT
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check -noinit -assert
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design -reset
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read_verilog <<EOT
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module top(input d, c, output reg [2:0] q);
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(* submod="bar" *) DFF s1(.D(d), .C(c), .Q(q[1]));
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DFF s2(.D(d), .C(c), .Q(q[0]));
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DFF s3(.D(d), .C(c), .Q(q[2]));
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endmodule
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EOT
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hierarchy -top top
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proc
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submod
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flatten
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read_verilog <<EOT
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module DFF(input D, C, output Q);
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endmodule
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EOT
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check -assert
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