mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 01:54:10 +00:00
Add test: 'Warning: ignoring initial value on non-register: \o'
This commit is contained in:
parent
613334d9dc
commit
e75ca29b19
|
@ -2,3 +2,13 @@ read_verilog -sv initval.v
|
|||
proc;;
|
||||
|
||||
sat -seq 10 -prove-asserts
|
||||
|
||||
design -reset
|
||||
read_verilog -icells <<EOT
|
||||
module top(input clk, i, output o, p);
|
||||
(* init = 1'bx *)
|
||||
wire p = o;
|
||||
$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
|
||||
endmodule
|
||||
EOT
|
||||
sat -seq 1
|
||||
|
|
Loading…
Reference in a new issue