mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 00:55:32 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
a46a7e8a67
19 changed files with 1771 additions and 969 deletions
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@ -34,11 +34,12 @@ proc
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equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd dffs # Constrain all select calls below inside the top module
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select -assert-count 1 t:DFFS
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select -assert-count 1 t:DFF
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select -assert-count 1 t:LUT2
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select -assert-count 4 t:IBUF
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select -assert-count 1 t:OBUF
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select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D
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select -assert-none t:DFF t:LUT2 t:IBUF t:OBUF %% t:* %D
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design -load read
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|
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224
tests/arch/gowin/init.v
Normal file
224
tests/arch/gowin/init.v
Normal file
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@ -0,0 +1,224 @@
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module myDFF (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK)
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Q <= D;
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endmodule
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module myDFFE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFE (positive clock edge; clock enable)
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module myDFFS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFS (positive clock edge; synchronous set)
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module myDFFSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable)
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module myDFFR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFR (positive clock edge; synchronous reset)
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module myDFFRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable)
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module myDFFP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFP (positive clock edge; asynchronous preset)
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module myDFFPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(posedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable)
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module myDFFC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFC (positive clock edge; asynchronous clear)
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module myDFFCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(posedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable)
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module myDFFN (output reg Q, input CLK, D);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK)
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Q <= D;
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endmodule
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module myDFFNE (output reg Q, input D, CLK, CE);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (CE)
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Q <= D;
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end
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endmodule // DFFNE (negative clock edge; clock enable)
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module myDFFNS (output reg Q, input D, CLK, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNS (negative clock edge; synchronous set)
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module myDFFNSE (output reg Q, input D, CLK, CE, SET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (SET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable)
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module myDFFNR (output reg Q, input D, CLK, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNR (negative clock edge; synchronous reset)
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module myDFFNRE (output reg Q, input D, CLK, CE, RESET);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK) begin
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if (RESET)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable)
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module myDFFNP (output reg Q, input D, CLK, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else
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Q <= D;
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end
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endmodule // DFFNP (negative clock edge; asynchronous preset)
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module myDFFNPE (output reg Q, input D, CLK, CE, PRESET);
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parameter [0:0] INIT = 1'b1;
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initial Q = INIT;
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always @(negedge CLK or posedge PRESET) begin
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if(PRESET)
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Q <= 1'b1;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable)
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module myDFFNC (output reg Q, input D, CLK, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else
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Q <= D;
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end
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endmodule // DFFNC (negative clock edge; asynchronous clear)
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module myDFFNCE (output reg Q, input D, CLK, CE, CLEAR);
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parameter [0:0] INIT = 1'b0;
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initial Q = INIT;
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always @(negedge CLK or posedge CLEAR) begin
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if(CLEAR)
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Q <= 1'b0;
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else if (CE)
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Q <= D;
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end
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endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable)
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74
tests/arch/gowin/init.ys
Normal file
74
tests/arch/gowin/init.ys
Normal file
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@ -0,0 +1,74 @@
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read_verilog init.v
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read_verilog -lib +/gowin/cells_sim.v
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design -save read
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proc
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flatten
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synth_gowin -run coarse:
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# check if all init values are handled
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check -assert -noinit
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# check if every flop mapped correctly
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select -assert-count 1 t:DFF
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:DFFCE
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select -assert-count 1 t:DFFE
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select -assert-count 1 t:DFFN
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select -assert-count 1 t:DFFNC
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select -assert-count 1 t:DFFNCE
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select -assert-count 1 t:DFFNE
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select -assert-count 1 t:DFFNP
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select -assert-count 1 t:DFFNPE
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select -assert-count 1 t:DFFNR
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select -assert-count 1 t:DFFNRE
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select -assert-count 1 t:DFFNS
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select -assert-count 1 t:DFFNSE
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select -assert-count 1 t:DFFP
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select -assert-count 1 t:DFFPE
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select -assert-count 1 t:DFFR
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select -assert-count 1 t:DFFRE
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select -assert-count 1 t:DFFS
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select -assert-count 1 t:DFFSE
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delete
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design -load read
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# these should synth to a flop with reset
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chparam -set INIT 1 myDFF myDFFN myDFFE myDFFNE
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# async should give a warning
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# sync should synth to a mux
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chparam -set INIT 0 myDFF*S* myDFF*P*
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chparam -set INIT 1 myDFF*R* myDFF*C*
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proc
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flatten
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synth_gowin -run coarse:
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# check the flops mapped as expected
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select -assert-count 1 t:DFF
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select -assert-count 1 t:DFFC
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select -assert-count 1 t:DFFCE
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select -assert-count 1 t:DFFE
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select -assert-count 1 t:DFFN
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select -assert-count 1 t:DFFNC
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select -assert-count 1 t:DFFNCE
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select -assert-count 1 t:DFFNE
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select -assert-count 1 t:DFFNP
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select -assert-count 1 t:DFFNPE
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select -assert-count 0 t:DFFNR
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select -assert-count 0 t:DFFNRE
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select -assert-count 2 t:DFFNS
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select -assert-count 2 t:DFFNSE
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||||
select -assert-count 1 t:DFFP
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||||
select -assert-count 1 t:DFFPE
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||||
select -assert-count 0 t:DFFR
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||||
select -assert-count 0 t:DFFRE
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||||
select -assert-count 2 t:DFFS
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||||
select -assert-count 2 t:DFFSE
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||||
select -assert-count 12 t:LUT2
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||||
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||||
# check the expected leftover init values
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||||
# this would happen if your reset value is not the initial value
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# which would be weird
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select -assert-count 8 a:init
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|
|
@ -1,3 +1,3 @@
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|||
../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v
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../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v
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iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v
|
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vvp -N ./test_macc
|
||||
|
|
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|||
|
|
@ -259,29 +259,35 @@ assign o = { 1'b1, 1'bx };
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|||
assign p = { 1'b1, 1'bx, 1'b0 };
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||||
endmodule
|
||||
|
||||
module abc9_test029(input clk1, clk2, d, output reg q1, q2);
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module abc9_test030(input [3:0] d, input en, output reg [3:0] q);
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always @*
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if (en)
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q <= d;
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||||
endmodule
|
||||
|
||||
module abc9_test031(input clk1, clk2, d, output reg q1, q2);
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||||
always @(posedge clk1) q1 <= d;
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||||
always @(negedge clk2) q2 <= q1;
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||||
endmodule
|
||||
|
||||
module abc9_test030(input clk, d, r, output reg q);
|
||||
module abc9_test032(input clk, d, r, output reg q);
|
||||
always @(posedge clk or posedge r)
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||||
if (r) q <= 1'b0;
|
||||
else q <= d;
|
||||
endmodule
|
||||
|
||||
module abc9_test031(input clk, d, r, output reg q);
|
||||
module abc9_test033(input clk, d, r, output reg q);
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||||
always @(negedge clk or posedge r)
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||||
if (r) q <= 1'b1;
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||||
else q <= d;
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||||
endmodule
|
||||
|
||||
module abc9_test033(input clk, d, output reg q1, q2);
|
||||
module abc9_test034(input clk, d, output reg q1, q2);
|
||||
always @(posedge clk) q1 <= d;
|
||||
always @(posedge clk) q2 <= q1;
|
||||
endmodule
|
||||
|
||||
module abc9_test034(input clk, d, output reg [1:0] q);
|
||||
module abc9_test035(input clk, d, output reg [1:0] q);
|
||||
always @(posedge clk) q[0] <= d;
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||||
always @(negedge clk) q[1] <= q[0];
|
||||
endmodule
|
||||
|
|
|
|||
99
tests/techmap/iopadmap.ys
Normal file
99
tests/techmap/iopadmap.ys
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
read_verilog << EOT
|
||||
module ibuf ((* iopad_external_pin *) input i, output o); endmodule
|
||||
module obuf (input i, (* iopad_external_pin *) output o); endmodule
|
||||
module obuft (input i, input oe, (* iopad_external_pin *) output o); endmodule
|
||||
module iobuf (input i, input oe, output o, (* iopad_external_pin *) inout io); endmodule
|
||||
|
||||
module a(input i, output o);
|
||||
assign o = i;
|
||||
endmodule
|
||||
|
||||
module b(input i, output o);
|
||||
assign o = i;
|
||||
ibuf b (.i(i), .o(o));
|
||||
endmodule
|
||||
|
||||
module c(input i, output o);
|
||||
obuf b (.i(i), .o(o));
|
||||
endmodule
|
||||
|
||||
module d(input i, oe, output o, o2, o3);
|
||||
assign o = oe ? i : 1'bz;
|
||||
assign o2 = o;
|
||||
assign o3 = ~o;
|
||||
endmodule
|
||||
|
||||
module e(input i, oe, inout io, output o2, o3);
|
||||
assign io = oe ? i : 1'bz;
|
||||
assign o2 = io;
|
||||
assign o3 = ~io;
|
||||
endmodule
|
||||
EOT
|
||||
|
||||
opt_clean
|
||||
tribuf
|
||||
simplemap
|
||||
iopadmap -bits -inpad ibuf o:i -outpad obuf i:o -toutpad obuft oe:i:o -tinoutpad iobuf oe:o:i:io
|
||||
opt_clean
|
||||
|
||||
select -assert-count 1 a/t:ibuf
|
||||
select -assert-count 1 a/t:obuf
|
||||
select -set ib w:i %a %co a/t:ibuf %i
|
||||
select -set ob w:o %a %ci a/t:obuf %i
|
||||
select -assert-count 1 @ib
|
||||
select -assert-count 1 @ob
|
||||
select -assert-count 1 @ib %co %co @ob %i
|
||||
|
||||
select -assert-count 1 b/t:ibuf
|
||||
select -assert-count 1 b/t:obuf
|
||||
select -set ib w:i %a %co b/t:ibuf %i
|
||||
select -set ob w:o %a %ci b/t:obuf %i
|
||||
select -assert-count 1 @ib
|
||||
select -assert-count 1 @ob
|
||||
select -assert-count 1 @ib %co %co @ob %i
|
||||
|
||||
select -assert-count 1 c/t:ibuf
|
||||
select -assert-count 1 c/t:obuf
|
||||
select -set ib w:i %a %co c/t:ibuf %i
|
||||
select -set ob w:o %a %ci c/t:obuf %i
|
||||
select -assert-count 1 @ib
|
||||
select -assert-count 1 @ob
|
||||
select -assert-count 1 @ib %co %co @ob %i
|
||||
|
||||
select -assert-count 2 d/t:ibuf
|
||||
select -assert-count 2 d/t:obuf
|
||||
select -assert-count 1 d/t:obuft
|
||||
select -set ib w:i %a %co d/t:ibuf %i
|
||||
select -set oeb w:oe %a %co d/t:ibuf %i
|
||||
select -set ob w:o %a %ci d/t:obuft %i
|
||||
select -set o2b w:o2 %a %ci d/t:obuf %i
|
||||
select -set o3b w:o3 %a %ci d/t:obuf %i
|
||||
select -assert-count 1 @ib
|
||||
select -assert-count 1 @oeb
|
||||
select -assert-count 1 @ob
|
||||
select -assert-count 1 @o2b
|
||||
select -assert-count 1 @o3b
|
||||
select -assert-count 1 @ib %co %co @ob %i
|
||||
select -assert-count 1 @oeb %co %co @ob %i
|
||||
select -assert-count 1 @ib %co %co @o2b %i
|
||||
select -assert-count 1 @ib %co %co t:$_NOT_ %i
|
||||
select -assert-count 1 @o3b %ci %ci t:$_NOT_ %i
|
||||
|
||||
select -assert-count 2 e/t:ibuf
|
||||
select -assert-count 2 e/t:obuf
|
||||
select -assert-count 1 e/t:iobuf
|
||||
select -set ib w:i %a %co e/t:ibuf %i
|
||||
select -set oeb w:oe %a %co e/t:ibuf %i
|
||||
select -set iob w:io %a %ci e/t:iobuf %i
|
||||
select -set o2b w:o2 %a %ci e/t:obuf %i
|
||||
select -set o3b w:o3 %a %ci e/t:obuf %i
|
||||
select -assert-count 1 @ib
|
||||
select -assert-count 1 @oeb
|
||||
select -assert-count 1 @iob
|
||||
select -assert-count 1 @o2b
|
||||
select -assert-count 1 @o3b
|
||||
select -assert-count 1 @ib %co %co @iob %i
|
||||
select -assert-count 1 @oeb %co %co @iob %i
|
||||
select -assert-count 1 @iob %co %co @o2b %i
|
||||
select -assert-count 1 @iob %co %co t:$_NOT_ %i
|
||||
select -assert-count 1 @o3b %ci %ci t:$_NOT_ %i
|
||||
Loading…
Add table
Add a link
Reference in a new issue