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16683 commits 121 branches 64 tags 50 MiB
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2364 commits

Author SHA1 Message Date
Gus Smith
c0f1654028 Expand test into three tests for three cases 
(1) no check, (2) check with warning, (3) check
with error. Previously the single test was not
testing all cases, as it was exiting after the
first error.
 2026-02-23 10:27:36 -08:00
Gus Smith
b454582f54 Detect undriven and error/warn 2026-02-20 11:00:59 -08:00
Emil J
74f7b0cf92
Merge pull request #5685 from chathhorn-galois/chathhorn/issue5684 
Fix segfault from shift with 0-width signed arg.
 2026-02-20 11:53:05 +01:00
Emil J
53509a9b2a
Merge pull request #5692 from YosysHQ/emil/modtools-fix-db-port-deletion 
modtools: fix database sanity
 2026-02-20 10:49:28 +01:00
Emil J. Tywoniak
abc7563a35 modtools: add ModIndex unit test 2026-02-18 22:15:44 +01:00
Miodrag Milanović
ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default 
Run unit tests on make test
 2026-02-13 15:02:50 +01:00
Chris Hathhorn
1e852cef16 Fix segfault from shift with 0-width signed arg. 
Fixes #5684.
 2026-02-12 22:03:42 -06:00
Miodrag Milanović
e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Miodrag Milanovic
cc79c6a761 Support building out of tree, but keep always in tests/unit 2026-02-12 12:17:07 +01:00
Maxim Kudinov
b055ea05fd gowin: dsp: Add mult inference tests 2026-02-12 14:12:32 +03:00
Gus Smith
7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Gus Smith
b0021e5b10 Add tests 2026-02-11 08:10:57 -08:00
Gus Smith
e3db8fee6f
Merge pull request #3459 from gs-jgj/feature_dsp48e1_presub 
Add support for subtract in preadder
 2026-02-11 08:02:18 -08:00
Gus Smith
8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Gus Smith
b04948a8cd Simplify test 2026-02-09 09:38:45 -08:00
Robert O'Callahan
34f8582725
Sanitize ABC global and per-run temporary directory names in logs 2026-02-07 12:12:13 +13:00
Emil J
1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Gus Smith
3f01d7a33a Add test 2026-02-03 14:41:08 -08:00
Emil J. Tywoniak
3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
Emil J
59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
Natalia
61b1c3c75a use run_pass in ecp5 add/sub test 2026-01-29 02:42:23 -08:00
Natalia
7439d2489e add assertion to run_pass test 2026-01-29 02:23:07 -08:00
Miodrag Milanović
43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Natalia
b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
nella
8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia
5a64fe2d91 tests/verific: assert module count explicitly 2026-01-28 04:21:13 -08:00
Natalia
8c2ef89732 tests/verific: import mixed -f list with -all 2026-01-28 04:13:04 -08:00
Natalia
74c601db0f tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00
Gus Smith
09ceadfde7
Merge pull request #4269 from povik/icells_not_derived 
Avoid `module_not_derived` on internal cells in techmap result
 2026-01-26 14:48:40 -08:00
Emil J
5b10c7f3c6
Merge pull request #4928 from XutaxKamay/main 
Add gatesi_mode to init gates under gates_mode in BLIF format
 2026-01-26 23:30:11 +01:00
nella
a3c9716f18 OptDff fix unit tests. 2026-01-26 22:35:25 +01:00
Emil J
673c8d1ae7
Merge pull request #5615 from rocallahan/remove-used-signals-updates 
Don't update `used_signals` for retained wires in `rmunused_module_signals`.
 2026-01-26 15:47:25 +01:00
nella
a75e0b2e92 opt_dff minor cleanup, added tests for comp var. 2026-01-26 14:24:01 +01:00
Robert O'Callahan
32e96605d4 Don't update used_signals for retained wires in rmunused_module_signals. 
These updates should not be necessary. In fact, if they were necessary, this code
would be buggy, because the results would depend on the order in which wires are traversed:
If wire A is retained, which causes an update to `used_signals`, which then causes wire B
to be retained when it otherwise wouldn't be, then we would get different results depending
on whether A is visited before B.

These updates will also make it difficult to process these wires in parallel.
 2026-01-24 03:41:18 +00:00
Emil J
f5ea73eb97
Merge pull request #5557 from nataliakokoromyti/lut2mux-word 
lut2mux: add -word option
 2026-01-23 17:24:41 +01:00
KrystalDelusion
125609105d
Merge pull request #5593 from RCoeurjoly/RCoeurjoly/5574_fix 
abc: handle ABC script errors instead of hanging
 2026-01-23 07:16:48 +13:00
Emil J
317a4d77c7
Merge pull request #5610 from nataliakokoromyti/upstream-debugon 
Add debugon pass for persistent debug logging
 2026-01-21 17:34:30 +01:00
Emil J
5e36503676
Merge pull request #5605 from nataliakokoromyti/opt_balance_tree 
Add opt_balance_tree pass
 2026-01-21 17:34:08 +01:00
Gus Smith
9ed56ac72c Mimic pattern of how other tests build plugins 
Seems like using --build isn't supported in CI
 2026-01-20 10:44:47 -08:00
Gus Smith
bd9dbea4ea Add -I 2026-01-20 10:07:44 -08:00
Gus Smith
0f6ef77775 Add test for ezCmdlineSAT 2026-01-20 09:28:00 -08:00
Gus Smith
491276983e Add test 2026-01-19 18:34:55 -08:00
Krystine Sherwin
0f478a5952
tests/bug5574: Fix for non threaded abc 2026-01-20 05:56:14 +13:00
Natalia
cf511628b0 modify generator for pyosys/wrappers.cc instead of headers 2026-01-18 02:11:09 -08:00
Natalia
ed64df737b Add -on/-off modes to debug pass 2026-01-15 12:07:26 -08:00
Natalia
d5e1647d11 fix tests with truncation issues 2026-01-14 18:03:30 -08:00
Natalia
fb864e91ee Add Design::run_pass() API for programmatic pass execution 
This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.

This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.

Example usage (from Python):
    design = ys.Design()
    # ... build or load design ...
    design.run_pass("hierarchy")
    design.run_pass("proc")
    design.run_pass("opt")

Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
 2026-01-14 17:35:45 -08:00
Emil J. Tywoniak
ddf3c6c8b7 blif: add -gatesi test 2026-01-14 21:41:56 +01:00
nella
763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella
210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00