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https://github.com/YosysHQ/yosys
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opt_dff minor cleanup, added tests for comp var.
This commit is contained in:
nella
parent
0e4282d442
commit
a75e0b2e92
3 changed files with 215 additions and 15 deletions
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@ -27,6 +27,7 @@
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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#include "passes/techmap/simplemap.h"
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#include "passes/opt/opt_dff_comp.h"
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#include <stdio.h>
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#include <stdlib.h>
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@ -55,7 +56,7 @@ struct OptDffWorker
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dict<SigBit, int> bitusers; // Signal sink count
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dict<SigBit, cell_int_t> bit2mux; // Signal bit to driving MUX
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// Eattern matching for clock enable
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// Pattern matching for clock enable
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typedef std::map<RTLIL::SigBit, bool> pattern_t; // Control signal -> required vals
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typedef std::set<pattern_t> patterns_t; // Alternative patterns (OR)
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typedef std::pair<RTLIL::SigBit, bool> ctrl_t; // Control signal
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@ -224,17 +225,6 @@ struct OptDffWorker
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{
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auto new_patterns = patterns;
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auto find_comp = [](const auto& left, const auto& right) -> std::optional<RTLIL::SigBit> {
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std::optional<RTLIL::SigBit> ret;
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for (const auto &pt: left) {
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if (right.count(pt.first) == 0) return {};
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if (right.at(pt.first) == pt.second) continue;
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if (ret) return {};
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ret = pt.first;
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}
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return ret;
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};
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// Remove complimentary patterns
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bool optimized;
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do {
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@ -243,7 +233,7 @@ struct OptDffWorker
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for (auto j = std::next(i, 1); j != patterns.end(); j++) {
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const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i;
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auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i;
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const auto complimentary_var = find_comp(left, right);
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const auto complimentary_var = find_complementary_pattern_var(left, right);
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if (complimentary_var && new_patterns.count(right)) {
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new_patterns.erase(right);
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@ -624,7 +614,7 @@ struct OptDffWorker
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ctrls_t resets;
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State reset_val = ff.has_srst ? ff.val_srst[i] : State::Sx;
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while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
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if (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
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cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
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if (GetSize(mbit.first->getPort(ID::S)) != 1)
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break;
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@ -712,7 +702,7 @@ struct OptDffWorker
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for (int i = 0; i < ff.width; i++) {
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ctrls_t enables;
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while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
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if (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
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cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
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if (GetSize(mbit.first->getPort(ID::S)) != 1)
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break;
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31
passes/opt/opt_dff_comp.h
Normal file
31
passes/opt/opt_dff_comp.h
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@ -0,0 +1,31 @@
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#ifndef OPT_DFF_COMP_H
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#define OPT_DFF_COMP_H
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#include "kernel/rtlil.h"
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#include <map>
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#include <optional>
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YOSYS_NAMESPACE_BEGIN
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typedef std::map<RTLIL::SigBit, bool> pattern_t;
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inline std::optional<RTLIL::SigBit> find_complementary_pattern_var(
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const pattern_t& left,
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const pattern_t& right
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) {
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std::optional<RTLIL::SigBit> ret;
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for (const auto &pt : left) {
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if (right.count(pt.first) == 0)
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return std::nullopt;
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if (right.at(pt.first) == pt.second)
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continue;
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if (ret)
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return std::nullopt;
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ret = pt.first;
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}
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return ret;
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}
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YOSYS_NAMESPACE_END
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#endif
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179
tests/unit/opt/optDffFindComplementaryPatternTest.cc
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179
tests/unit/opt/optDffFindComplementaryPatternTest.cc
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@ -0,0 +1,179 @@
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#include <gtest/gtest.h>
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#include "passes/opt/opt_dff_comp.h"
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YOSYS_NAMESPACE_BEGIN
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class FindComplementaryPatternVarTest : public ::testing::Test {
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protected:
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RTLIL::Design *design;
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RTLIL::Module *module;
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RTLIL::Wire *wire_a;
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RTLIL::Wire *wire_b;
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RTLIL::Wire *wire_c;
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RTLIL::Wire *bus;
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void SetUp() override {
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design = new RTLIL::Design;
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module = design->addModule(ID(test_module));
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wire_a = module->addWire(ID(a));
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wire_b = module->addWire(ID(b));
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wire_c = module->addWire(ID(c));
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bus = module->addWire(ID(bus), 4);
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}
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void TearDown() override {
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delete design;
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}
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RTLIL::SigBit bit(RTLIL::Wire *w, int offset = 0) {
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return RTLIL::SigBit(w, offset);
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}
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};
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TEST_F(FindComplementaryPatternVarTest, EmptyPatterns) {
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pattern_t left, right;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, IdenticalSingleVar) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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right[bit(wire_a)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, ComplementarySingleVar) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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right[bit(wire_a)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_a));
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}
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TEST_F(FindComplementaryPatternVarTest, MissingKeyInRight) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, TwoVarsOneComplementary) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = true;
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right[bit(wire_b)] = true;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_b));
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}
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TEST_F(FindComplementaryPatternVarTest, TwoVarsBothComplementary) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = false;
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right[bit(wire_b)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, LeftSubsetOfRight) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = true;
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right[bit(wire_b)] = true;
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right[bit(wire_c)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_b));
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}
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TEST_F(FindComplementaryPatternVarTest, ThreeVarsAllSame) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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left[bit(wire_c)] = true;
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right[bit(wire_a)] = true;
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right[bit(wire_b)] = false;
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right[bit(wire_c)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, PracticalPatternSimplification) {
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pattern_t pattern1, pattern2;
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pattern1[bit(bus, 0)] = true;
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pattern1[bit(bus, 1)] = true;
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pattern2[bit(bus, 0)] = true;
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pattern2[bit(bus, 1)] = false;
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auto result = find_complementary_pattern_var(pattern1, pattern2);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(bus, 1));
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// Swapped args
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auto result2 = find_complementary_pattern_var(pattern2, pattern1);
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ASSERT_TRUE(result2.has_value());
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EXPECT_EQ(result2.value(), bit(bus, 1));
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}
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TEST_F(FindComplementaryPatternVarTest, MuxTreeClockEnableDetection) {
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pattern_t feedback_path1, feedback_path2;
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feedback_path1[bit(wire_a)] = true;
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feedback_path1[bit(wire_b)] = true;
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feedback_path2[bit(wire_a)] = true;
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feedback_path2[bit(wire_b)] = false;
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auto comp = find_complementary_pattern_var(feedback_path1, feedback_path2);
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ASSERT_TRUE(comp.has_value());
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EXPECT_EQ(comp.value(), bit(wire_b));
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pattern_t simplified = feedback_path1;
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simplified.erase(comp.value());
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EXPECT_EQ(simplified.size(), 1);
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EXPECT_TRUE(simplified.count(bit(wire_a)));
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EXPECT_TRUE(simplified[bit(wire_a)]);
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}
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TEST_F(FindComplementaryPatternVarTest, AsymmetricPatterns) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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right[bit(wire_a)] = false;
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right[bit(wire_b)] = true;
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right[bit(wire_c)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_a));
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}
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TEST_F(FindComplementaryPatternVarTest, WireOffsetDistinction) {
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pattern_t left, right;
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left[bit(bus, 0)] = true;
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left[bit(bus, 1)] = false;
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right[bit(bus, 0)] = true;
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right[bit(bus, 1)] = true;
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right[bit(bus, 2)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(bus, 1));
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}
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YOSYS_NAMESPACE_END
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