mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-02 07:16:19 +00:00
Code Activity

tests/verific: ensure mixed -f requires VHDL unit

Browse source
This commit is contained in:
Natalia 2026-01-28 22:46:10 -08:00
parent 5a64fe2d91
commit b6c148f84a
2 changed files with 3 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

3
tests/verific/mixed_flist.sv
View file

@ -1,3 +1,4 @@
module sv_top(input logic a, output logic y);
assign y = a;
// Instantiates VHDL entity to ensure mixed -f list is required
vhdl_mod u_vhdl(.a(a), .y(y));
endmodule

3
tests/verific/mixed_flist.ys
View file

@ -1,4 +1,3 @@
verific -f -sv mixed_flist.flist
verific -import -all
verific -import sv_top
select -assert-mod-count 1 sv_top
select -assert-mod-count 2 =*