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Merge pull request #5670 from max-kudinov/gowin_mult
Gowin: Add DSP inference for GW1N and GW2A
This commit is contained in:
Miodrag Milanović
GitHub
commit
e4b32d6aae
5 changed files with 233 additions and 10 deletions
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@ -12,3 +12,4 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map_gw5a.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
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$(eval $(call add_share_file,share/gowin,techlibs/gowin/dsp_map.v))
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70
techlibs/gowin/dsp_map.v
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70
techlibs/gowin/dsp_map.v
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@ -0,0 +1,70 @@
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module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT9X9 __TECHMAP_REPLACE__ (
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.CLK(1'b0),
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.CE(1'b0),
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.RESET(1'b0),
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.A(A),
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.SIA({A_WIDTH{1'b0}}),
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.ASEL(1'b0),
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.ASIGN(A_SIGNED ? 1'b1 : 1'b0),
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.B(B),
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.SIB({B_WIDTH{1'b0}}),
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.BSEL(1'b0),
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.BSIGN(B_SIGNED ? 1'b1 : 1'b0),
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.DOUT(Y)
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);
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endmodule
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module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT18X18 __TECHMAP_REPLACE__ (
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.CLK(1'b0),
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.CE(1'b0),
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.RESET(1'b0),
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.A(A),
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.SIA({A_WIDTH{1'b0}}),
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.ASEL(1'b0),
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.ASIGN(A_SIGNED ? 1'b1 : 1'b0),
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.B(B),
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.SIB({B_WIDTH{1'b0}}),
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.BSEL(1'b0),
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.BSIGN(B_SIGNED ? 1'b1 : 1'b0),
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.DOUT(Y)
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);
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endmodule
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module \$__MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 36;
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parameter Y_WIDTH = 72;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT36X36 __TECHMAP_REPLACE__ (
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.CLK(1'b0),
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.RESET(1'b0),
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.CE(1'b0),
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.A(A),
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.ASIGN(A_SIGNED ? 1'b1 : 1'b0),
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.B(B),
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.BSIGN(B_SIGNED ? 1'b1 : 1'b0),
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.DOUT(Y)
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);
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endmodule
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@ -29,6 +29,21 @@ struct SynthGowinPass : public ScriptPass
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{
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SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
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struct DSPRule {
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int a_maxwidth;
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int b_maxwidth;
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int a_minwidth;
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int b_minwidth;
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std::string prim;
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};
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const std::vector<DSPRule> dsp_rules = {
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{36, 36, 22, 22, "$__MUL36X36"},
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{18, 18, 10, 4, "$__MUL18X18"},
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{18, 18, 4, 10, "$__MUL18X18"},
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{9, 9, 4, 4, "$__MUL9X9"},
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};
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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@ -97,13 +112,16 @@ struct SynthGowinPass : public ScriptPass
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log(" -setundef\n");
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log(" set undriven wires and parameters to zero\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not infer DSP multipliers\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_opt, vout_file, json_file, family;
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bool retime, nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, abc9, noiopads, noalu, no_rw_check, setundef;
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bool retime, nobram, nolutram, flatten, nodffe, strict_gw5a_dffs, nowidelut, abc9, noiopads, noalu, no_rw_check, setundef, nodsp;
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void clear_flags() override
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{
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@ -123,6 +141,7 @@ struct SynthGowinPass : public ScriptPass
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noalu = false;
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no_rw_check = false;
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setundef = false;
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nodsp = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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@ -209,6 +228,10 @@ struct SynthGowinPass : public ScriptPass
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setundef = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -239,17 +262,40 @@ struct SynthGowinPass : public ScriptPass
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
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}
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if (flatten && check_label("flatten", "(unless -noflatten)"))
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{
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run("proc");
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run("flatten");
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run("tribuf -logic");
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run("deminout");
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}
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if (check_label("coarse"))
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{
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run("synth -run coarse" + no_rw_check_opt);
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run("proc");
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if (flatten || help_mode)
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run("flatten", "(unless -noflatten)");
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run("tribuf -logic");
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run("deminout");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt -nodffe -nosdff");
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run("fsm");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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run("share");
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if (help_mode) {
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run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp and if -family gw1n or gw2a)");
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run("techmap -map +/gowin/dsp_map.v", "(unless -nodsp and if -family gw1n or gw2a)");
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} else if (!nodsp && (family == "gw1n" || family == "gw2a")) {
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for (const auto &rule : dsp_rules) {
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run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
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rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim));
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run("chtype -set $mul t:$__soft_mul");
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}
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run("techmap -map +/gowin/dsp_map.v");
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}
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run("alumacc");
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run("opt");
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run("memory -nomap" + no_rw_check_opt);
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run("opt_clean");
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}
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if (check_label("map_ram"))
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53
tests/arch/gowin/mul_gw1n.ys
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53
tests/arch/gowin/mul_gw1n.ys
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@ -0,0 +1,53 @@
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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# equivalence checking is somewhat slow (and missing simulation models)
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synth_gowin -family gw1n
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT9X9
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# Make sure that DSPs are not inferred with -nodsp option
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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synth_gowin -family gw1n -nodsp
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cd top # Constrain all select calls below inside the top module
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select -assert-none t:MULT9X9
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
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hierarchy -top top
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proc
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synth_gowin -family gw1n
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X18
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT36X36
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# We end up with two 18x18 multipliers
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# 36x36 min width is 22
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MULT18X18
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53
tests/arch/gowin/mul_gw2a.ys
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53
tests/arch/gowin/mul_gw2a.ys
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@ -0,0 +1,53 @@
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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# equivalence checking is somewhat slow (and missing simulation models)
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT9X9
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# Make sure that DSPs are not inferred with -nodsp option
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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synth_gowin -family gw2a -nodsp
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cd top # Constrain all select calls below inside the top module
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select -assert-none t:MULT9X9
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
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hierarchy -top top
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proc
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X18
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT36X36
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# We end up with two 18x18 multipliers
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# 36x36 min width is 22
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_gowin -family gw2a
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cd top # Constrain all select calls below inside the top module
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select -assert-count 2 t:MULT18X18
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