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Fix segfault from shift with 0-width signed arg.

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Fixes #5684.
This commit is contained in:
Chris Hathhorn 2026-02-12 21:51:38 -06:00
parent bfd1401b32
commit 1e852cef16
2 changed files with 50 additions and 1 deletions
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2
kernel/calc.cc
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@ -291,7 +291,7 @@ static RTLIL::Const const_shift_worker(const RTLIL::Const &arg1, const RTLIL::Co
if (pos < 0)
result.set(i, vacant_bits);
else if (pos >= BigInteger(GetSize(arg1)))
result.set(i, sign_ext ? arg1.back() : vacant_bits);
result.set(i, sign_ext && !arg1.empty() ? arg1.back() : vacant_bits);
else
result.set(i, arg1[pos.toInt()]);
}

49
tests/various/const_shift_empty_arg.ys Normal file
View file

@ -0,0 +1,49 @@
# Regression test for #5684: const_shift_worker must not crash when arg1 is
# empty.
read_json << EOF
{
"modules": {
"sshl": {
"cells": {
"sshlCell": {
"connections": {
"A": [],
"B": [3],
"Y": [1]
},
"parameters": {
"A_SIGNED": "1",
"A_WIDTH": "0",
"B_SIGNED": "0",
"B_WIDTH": "1",
"Y_WIDTH": "1"
},
"port_directions": {
"A": "input",
"B": "input",
"Y": "output"
},
"type": "$sshl"
}
},
"ports": {
"A": {
"bits": [],
"direction": "input"
},
"B": {
"bits": [3],
"direction": "input"
},
"Y": {
"bits": [1],
"direction": "output"
}
}
}
}
}
EOF
eval -set B 0 -show Y sshl